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Searched refs:InstrStage (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCSchedule440.td108 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
109 InstrStage<1, [P440_IRACC, P440_LRACC]>,
110 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
111 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
112 InstrStage<1, [P440_IWB, P440_JWB]>],
116 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
117 InstrStage<1, [P440_IRACC, P440_LRACC]>,
118 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
119 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
120 InstrStage<1, [P440_IWB, P440_JWB]>],
[all …]
DPPCScheduleP7.td83 InstrItinData<IIC_IntSimple , [InstrStage<1, [P7_DU1, P7_DU2,
85 InstrStage<1, [P7_FX1, P7_FX2,
88 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
90 InstrStage<1, [P7_FX1, P7_FX2]>],
92 InstrItinData<IIC_IntISEL, [InstrStage<1, [P7_DU1], 0>,
93 InstrStage<1, [P7_FX1, P7_FX2], 0>,
94 InstrStage<1, [P7_BRU]>],
96 InstrItinData<IIC_IntCompare , [InstrStage<1, [P7_DU1, P7_DU2,
98 InstrStage<1, [P7_FX1, P7_FX2]>],
101 InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>,
[all …]
DPPCScheduleP8.td58 InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
60 InstrStage<1, [P8_FXU1, P8_FXU2,
64 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
66 InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
69 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
70 InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
71 InstrStage<1, [P8_BRU]>],
73 InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
75 InstrStage<1, [P8_FXU1, P8_FXU2]>],
77 InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
[all …]
DPPCScheduleE5500.td51 InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
52 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
56 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
57 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
61 InstrItinData<IIC_IntISEL, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
62 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
67 InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
68 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
72 InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
73 InstrStage<1, [E5500_CFX_0], 0>,
[all …]
DPPCScheduleG4.td28 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
29 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
30 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4_IU1, G4_IU2]>]>,
31 InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>,
32 InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>,
33 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>,
34 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>,
35 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>,
36 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>,
37 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>,
[all …]
DPPCScheduleE500mc.td47 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
48 InstrStage<1, [E500_SFX0, E500_SFX1]>],
52 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
53 InstrStage<1, [E500_SFX0, E500_SFX1]>],
57 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
58 InstrStage<1, [E500_SFX0, E500_SFX1]>],
63 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
64 InstrStage<1, [E500_SFX0, E500_SFX1]>],
68 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
69 InstrStage<1, [E500_CFX_0], 0>,
[all …]
DPPCScheduleG5.td29 InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
30 InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>,
31 InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>,
32 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
33 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
34 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
35 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
36 InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
37 InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>,
38 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>,
[all …]
DPPCScheduleG4Plus.td30 InstrItinData<IIC_IntSimple , [InstrStage<1, [G4P_IU1, G4P_IU2,
32 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4P_IU1, G4P_IU2,
34 InstrItinData<IIC_IntCompare , [InstrStage<1, [G4P_IU1, G4P_IU2,
36 InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>,
37 InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>,
38 InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>,
39 InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>,
40 InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>,
41 InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>,
42 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>,
[all …]
DPPCScheduleA2.td28 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
30 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
32 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
34 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
36 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
38 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
40 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
42 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
44 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
46 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
[all …]
DPPCScheduleG3.td23 InstrItinData<IIC_IntSimple , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
24 InstrItinData<IIC_IntGeneral , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
25 InstrItinData<IIC_IntCompare , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
26 InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>,
27 InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>,
28 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>,
29 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>,
30 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>,
31 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>,
32 InstrItinData<IIC_IntRotate , [InstrStage<1, [G3_IU1, G3_IU2]>]>,
[all …]
/external/llvm/lib/Target/X86/
DX86ScheduleAtom.td29 // InstrItinData<class, [InstrStage<N, [P0]>] >,
31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
36 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
37 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
38 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
39 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
41 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
42 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
43 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
[all …]
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
[all …]
DARMScheduleA9.td46 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
48 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
49 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
50 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
51 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
52 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
53 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
54 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
55 InstrStage<1, [A9_ALU0, A9_ALU1]>,
[all …]
DARMScheduleV6.td25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
34 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
35 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,
36 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
37 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,
40 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
[all …]
DARMScheduleSwift.td44 InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
45 InstrStage<1, [SW_ALU0, SW_ALU1]>],
47 InstrItinData<IIC_iMOVr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
48 InstrStage<1, [SW_ALU0, SW_ALU1]>],
50 InstrItinData<IIC_iMOVsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
51 InstrStage<1, [SW_ALU0, SW_ALU1]>],
53 InstrItinData<IIC_iMOVsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
54 InstrStage<1, [SW_ALU0, SW_ALU1]>],
56 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
57 InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
[all …]
/external/llvm/lib/Target/Mips/
DMipsSchedule.td174 InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
175 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
176 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
177 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
178 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
179 InstrItinData<II_BADDU , [InstrStage<1, [ALU]>]>,
180 InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
181 InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
182 InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
183 InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>,
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV4.td100 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
102 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
104 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
106 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
108 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
110 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
114 InstrItinData<ALU64_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
115 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
116 InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
[all …]
/external/llvm/lib/Target/R600/
DR600Schedule.td32 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
33 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
34 InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
35 InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>,
36 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
44 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
45 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
46 InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
47 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp52 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
53 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
135 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
154 case InstrStage::Required: in getHazardType()
158 case InstrStage::Reserved: in getHazardType()
195 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction()
206 case InstrStage::Required: in EmitInstruction()
210 case InstrStage::Reserved: in EmitInstruction()
223 if (IS->getReservationKind() == InstrStage::Required) in EmitInstruction()
DDFAPacketizer.cpp68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); in canReserveResources()
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); in reserveResources()
/external/llvm/include/llvm/MC/
DMCInstrItineraries.h59 struct InstrStage { struct
112 const InstrStage *Stages; ///< Array of stages selected
123 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S, in InstrItineraryData()
138 const InstrStage *beginStage(unsigned ItinClassIndx) const { in beginStage()
144 const InstrStage *endStage(unsigned ItinClassIndx) const { in endStage()
160 for (const InstrStage *IS = beginStage(ItinClassIndx), in getStageLatency()
DMCSubtargetInfo.h42 const InstrStage *Stages; // Instruction itinerary stages
55 const InstrStage *IS,
/external/mesa3d/src/gallium/drivers/radeon/
DR600Schedule.td31 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
32 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
33 InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
34 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
/external/llvm/include/llvm/Target/
DTargetItinerary.td53 // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
54 // InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit
57 class InstrStage<int cycles, list<FuncUnit> units,
99 // InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
100 // InstrStage<1, [A9_AGU]>],
102 // InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>],
110 class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
115 list<InstrStage> Stages = stages;
/external/llvm/lib/MC/
DMCSubtargetInfo.cpp45 const InstrStage *IS, in InitMCSubtargetInfo()

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