Searched refs:IsLP64 (Results 1 – 4 of 4) sorted by relevance
/external/llvm/lib/Target/X86/ |
D | X86FrameLowering.cpp | 88 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { in getSUBriOpcode() argument 89 if (IsLP64) { in getSUBriOpcode() 100 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { in getADDriOpcode() argument 101 if (IsLP64) { in getADDriOpcode() 120 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) { in getANDriOpcode() argument 121 if (IsLP64) { in getANDriOpcode() 131 static unsigned getLEArOpcode(unsigned IsLP64) { in getLEArOpcode() argument 132 return IsLP64 ? X86::LEA64r : X86::LEA32r; in getLEArOpcode() 1557 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) { in GetScratchRegister() argument 1569 if (IsLP64) in GetScratchRegister() [all …]
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D | X86InstrCompiler.td | 68 Requires<[IsLP64]>; 72 Requires<[IsLP64]>; 75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>; 1005 Requires<[IsLP64]>; 1009 Requires<[IsLP64]>;
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D | X86ISelLowering.cpp | 18598 const bool IsLP64 = Subtarget->isTarget64BitLP64(); in EmitLoweredSegAlloca() local 18601 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30; in EmitLoweredSegAlloca() 18632 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP; in EmitLoweredSegAlloca() 18648 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) in EmitLoweredSegAlloca() 18650 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr)) in EmitLoweredSegAlloca() 18666 if (IsLP64) { in EmitLoweredSegAlloca() 18697 .addReg(IsLP64 ? X86::RAX : X86::EAX); in EmitLoweredSegAlloca()
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D | X86InstrInfo.td | 794 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
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