Searched refs:IsPostRA (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 109 bool IsPostRA);
116 MachineLoopInfo &MLI, bool IsPostRA) in DefaultVLIWScheduler() argument
117 : ScheduleDAGInstrs(MF, &MLI, IsPostRA) { in DefaultVLIWScheduler()
128 MachineLoopInfo &MLI, bool IsPostRA) in VLIWPacketizerList() argument
132 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA); in VLIWPacketizerList()
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| D | ScheduleDAGInstrs.cpp | 57 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags), in ScheduleDAGInstrs()
59 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); in ScheduleDAGInstrs()
61 assert(!(IsPostRA && MRI.getNumVirtRegs()) && in ScheduleDAGInstrs()
230 assert(!IsPostRA && "Virtual register encountered after regalloc."); in addSchedBarrierDeps()
835 assert(!IsPostRA && "Virtual register encountered!"); in buildSchedGraph()
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| D | MachineScheduler.cpp | 387 bool IsPostRA) { in isSchedBoundary() argument
394 bool IsPostRA = Scheduler.isPostRA(); in scheduleRegions() local
432 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) { in scheduleRegions()
443 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA)) in scheduleRegions()
2149 bool IsPostRA, in setPolicy() argument
2189 if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) { in setPolicy()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 88 bool IsPostRA; variable
163 bool isPostRA() const { return IsPostRA; } in isPostRA()
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| D | MachineScheduler.h | 251 bool IsPostRA) in ScheduleDAGMI() argument
252 : ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA, in ScheduleDAGMI()
253 /*RemoveKillFlags=*/IsPostRA, C->LIS), in ScheduleDAGMI()
834 void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
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| D | DFAPacketizer.h | 109 VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA);
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