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Searched refs:IssueWidth (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp36 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), in ScoreboardHazardRecognizer()
81 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
112 if (IssueWidth == 0) in atIssueLimit()
115 return IssueCount == IssueWidth; in atIssueLimit()
DTargetSchedule.cpp63 ResourceLCM = SchedModel.IssueWidth; in init()
69 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
/external/llvm/include/llvm/CodeGen/
DScoreboardHazardRecognizer.h98 unsigned IssueWidth; variable
DTargetSchedule.h85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
/external/llvm/include/llvm/MC/
DMCSchedule.h139 unsigned IssueWidth; member
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td162 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
DPPCScheduleG5.td120 let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
DPPCScheduleE500mc.td313 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
DPPCScheduleE5500.td373 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
DPPCScheduleP8.td386 let IssueWidth = 8; // up to 8 instructions dispatched per cycle.
DPPCScheduleP7.td376 let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
DPPCSchedule440.td599 let IssueWidth = 2; // 2 instructions are dispatched per cycle.
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV4.td196 let IssueWidth = 4;
/external/llvm/include/llvm/Target/
DTargetItinerary.td90 // global IssueWidth property, which constrains the number of microops
DTargetSchedule.td78 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
269 // against the processor's IssueWidth limit. If an instruction can
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td18 let IssueWidth = 2;
DX86Schedule.td621 // IssueWidth is analogous to the number of decode units. Core and its
638 let IssueWidth = 4;
DX86SchedSandyBridge.td19 let IssueWidth = 4;
DX86ScheduleBtVer2.td19 let IssueWidth = 2;
DX86ScheduleAtom.td538 let IssueWidth = 2; // Allows 2 instructions per scheduling group.
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp320 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) { in reserveResources()
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td21 // Therefore, IssueWidth is set to the narrower of the two at three, while still
25 let IssueWidth = 3; // 3-way decode and dispatch
DAArch64SchedA53.td21 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
DAArch64SchedCyclone.td16 let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td1067 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.

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