| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 102 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
110 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
127 multiclass ABSS_M<string opstr, InstrItinClass Itin,
129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
[all …]
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| D | MicroMipsInstrInfo.td | 231 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
234 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
239 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
242 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
263 InstrItinClass Itin = NoItinerary> :
266 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
273 InstrItinClass Itin = NoItinerary,
277 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
282 InstrItinClass Itin = NoItinerary> :
284 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
[all …]
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| D | MipsCondMov.td | 20 InstrItinClass Itin> :
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
28 InstrItinClass Itin> :
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr> {
35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
40 Itin, FrmFR, opstr> {
45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
50 Itin, FrmFR, opstr> {
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| D | MipsInstrInfo.td | 587 InstrItinClass Itin = NoItinerary,
591 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
599 InstrItinClass Itin = NoItinerary,
605 Itin, FrmI, opstr> {
655 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
657 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
664 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
666 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
674 InstrItinClass Itin> :
677 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 207 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize() local
212 Top.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG); in initialize()
213 Bot.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG); in initialize()
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| D | HexagonInstrInfoV4.td | 2610 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2615 "$Rd = $Rx", Itin> {
2635 InstrItinClass Itin> {
2636 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2637 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 2379 const InstrItineraryData *Itin = SchedModel->getInstrItineraries(); in initialize() local
2383 Itin, DAG); in initialize()
2388 Itin, DAG); in initialize()
2913 const InstrItineraryData *Itin = SchedModel->getInstrItineraries(); in initialize() local
2917 Itin, DAG); in initialize()
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