Searched refs:LD4 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/CodeGen/ARM/ |
| D | ldrd-memoper.ll | 8 ; CHECK: Formed {{.*}} t2LDRD{{.*}} mem:LD4[%0] LD4[%0+4]
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| D | subreg-remat.ll | 8 ; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vre…
34 ; %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>; mem:LD4[ConstantPo…
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| /external/llvm/test/CodeGen/X86/ |
| D | 2010-05-12-FastAllocKills.ll | 9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
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| /external/webp/src/dsp/ |
| D | enc.c | 370 static void LD4(uint8_t* dst, const uint8_t* top) { in LD4() function
495 LD4(I4LD4 + dst, top); in Intra4Preds()
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| D | dec.c | 295 static void LD4(uint8_t *dst) { // Down-Left in LD4() function
460 DC4, TM4, VE4, HE4, RD4, VR4, LD4, VL4, HD4, HU4
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 580 // FCVT Rd, S/D = V6+LD4: 10 cycles
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| D | AArch64InstrInfo.td | 4741 defm LD4 : SIMDLd4Multiple<"ld4">;
4794 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4795 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4796 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4797 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4863 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
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| /external/vixl/doc/ |
| D | supported-instructions.md | 2580 ### LD4 ### subsection
2592 ### LD4 ### subsection
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 815 def LD4 : WInst<"vld4", "4c", "QUlQldQdPlQPl">;
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