1 //===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
11 #include "SIDefines.h"
12 #include "llvm/ADT/APFloat.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/Debug.h"
33 
34 using namespace llvm;
35 
36 namespace {
37 
38 struct OptionalOperand;
39 
40 class AMDGPUOperand : public MCParsedAsmOperand {
41   enum KindTy {
42     Token,
43     Immediate,
44     Register,
45     Expression
46   } Kind;
47 
48   SMLoc StartLoc, EndLoc;
49 
50 public:
AMDGPUOperand(enum KindTy K)51   AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {}
52 
53   MCContext *Ctx;
54 
55   enum ImmTy {
56     ImmTyNone,
57     ImmTyDSOffset0,
58     ImmTyDSOffset1,
59     ImmTyGDS,
60     ImmTyOffset,
61     ImmTyGLC,
62     ImmTySLC,
63     ImmTyTFE,
64     ImmTyClamp,
65     ImmTyOMod
66   };
67 
68   struct TokOp {
69     const char *Data;
70     unsigned Length;
71   };
72 
73   struct ImmOp {
74     bool IsFPImm;
75     ImmTy Type;
76     int64_t Val;
77   };
78 
79   struct RegOp {
80     unsigned RegNo;
81     int Modifiers;
82     const MCRegisterInfo *TRI;
83   };
84 
85   union {
86     TokOp Tok;
87     ImmOp Imm;
88     RegOp Reg;
89     const MCExpr *Expr;
90   };
91 
addImmOperands(MCInst & Inst,unsigned N) const92   void addImmOperands(MCInst &Inst, unsigned N) const {
93     Inst.addOperand(MCOperand::CreateImm(getImm()));
94   }
95 
getToken() const96   StringRef getToken() const {
97     return StringRef(Tok.Data, Tok.Length);
98   }
99 
addRegOperands(MCInst & Inst,unsigned N) const100   void addRegOperands(MCInst &Inst, unsigned N) const {
101     Inst.addOperand(MCOperand::CreateReg(getReg()));
102   }
103 
addRegOrImmOperands(MCInst & Inst,unsigned N) const104   void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
105     if (isReg())
106       addRegOperands(Inst, N);
107     else
108       addImmOperands(Inst, N);
109   }
110 
addRegWithInputModsOperands(MCInst & Inst,unsigned N) const111   void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
112     Inst.addOperand(MCOperand::CreateImm(Reg.Modifiers));
113     addRegOperands(Inst, N);
114   }
115 
addSoppBrTargetOperands(MCInst & Inst,unsigned N) const116   void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
117     if (isImm())
118       addImmOperands(Inst, N);
119     else {
120       assert(isExpr());
121       Inst.addOperand(MCOperand::CreateExpr(Expr));
122     }
123   }
124 
defaultTokenHasSuffix() const125   bool defaultTokenHasSuffix() const {
126     StringRef Token(Tok.Data, Tok.Length);
127 
128     return Token.endswith("_e32") || Token.endswith("_e64");
129   }
130 
isToken() const131   bool isToken() const override {
132     return Kind == Token;
133   }
134 
isImm() const135   bool isImm() const override {
136     return Kind == Immediate;
137   }
138 
isInlineImm() const139   bool isInlineImm() const {
140     float F = BitsToFloat(Imm.Val);
141     // TODO: Add 0.5pi for VI
142     return isImm() && ((Imm.Val <= 64 && Imm.Val >= -16) ||
143            (F == 0.0 || F == 0.5 || F == -0.5 || F == 1.0 || F == -1.0 ||
144            F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0));
145   }
146 
isDSOffset0() const147   bool isDSOffset0() const {
148     assert(isImm());
149     return Imm.Type == ImmTyDSOffset0;
150   }
151 
isDSOffset1() const152   bool isDSOffset1() const {
153     assert(isImm());
154     return Imm.Type == ImmTyDSOffset1;
155   }
156 
getImm() const157   int64_t getImm() const {
158     return Imm.Val;
159   }
160 
getImmTy() const161   enum ImmTy getImmTy() const {
162     assert(isImm());
163     return Imm.Type;
164   }
165 
isReg() const166   bool isReg() const override {
167     return Kind == Register && Reg.Modifiers == -1;
168   }
169 
isRegWithInputMods() const170   bool isRegWithInputMods() const {
171     return Kind == Register && Reg.Modifiers != -1;
172   }
173 
setModifiers(unsigned Mods)174   void setModifiers(unsigned Mods) {
175     assert(isReg());
176     Reg.Modifiers = Mods;
177   }
178 
getReg() const179   unsigned getReg() const override {
180     return Reg.RegNo;
181   }
182 
isRegOrImm() const183   bool isRegOrImm() const {
184     return isReg() || isImm();
185   }
186 
isRegClass(unsigned RCID) const187   bool isRegClass(unsigned RCID) const {
188     return Reg.TRI->getRegClass(RCID).contains(getReg());
189   }
190 
isSCSrc32() const191   bool isSCSrc32() const {
192     return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
193   }
194 
isSSrc32() const195   bool isSSrc32() const {
196     return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
197   }
198 
isSSrc64() const199   bool isSSrc64() const {
200     return isImm() || isInlineImm() ||
201            (isReg() && isRegClass(AMDGPU::SReg_64RegClassID));
202   }
203 
isVCSrc32() const204   bool isVCSrc32() const {
205     return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
206   }
207 
isVCSrc64() const208   bool isVCSrc64() const {
209     return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
210   }
211 
isVSrc32() const212   bool isVSrc32() const {
213     return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
214   }
215 
isVSrc64() const216   bool isVSrc64() const {
217     return isImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
218   }
219 
isMem() const220   bool isMem() const override {
221     return false;
222   }
223 
isExpr() const224   bool isExpr() const {
225     return Kind == Expression;
226   }
227 
isSoppBrTarget() const228   bool isSoppBrTarget() const {
229     return isExpr() || isImm();
230   }
231 
getStartLoc() const232   SMLoc getStartLoc() const override {
233     return StartLoc;
234   }
235 
getEndLoc() const236   SMLoc getEndLoc() const override {
237     return EndLoc;
238   }
239 
print(raw_ostream & OS) const240   void print(raw_ostream &OS) const override { }
241 
CreateImm(int64_t Val,SMLoc Loc,enum ImmTy Type=ImmTyNone,bool IsFPImm=false)242   static std::unique_ptr<AMDGPUOperand> CreateImm(int64_t Val, SMLoc Loc,
243                                                   enum ImmTy Type = ImmTyNone,
244                                                   bool IsFPImm = false) {
245     auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
246     Op->Imm.Val = Val;
247     Op->Imm.IsFPImm = IsFPImm;
248     Op->Imm.Type = Type;
249     Op->StartLoc = Loc;
250     Op->EndLoc = Loc;
251     return Op;
252   }
253 
CreateToken(StringRef Str,SMLoc Loc,bool HasExplicitEncodingSize=true)254   static std::unique_ptr<AMDGPUOperand> CreateToken(StringRef Str, SMLoc Loc,
255                                            bool HasExplicitEncodingSize = true) {
256     auto Res = llvm::make_unique<AMDGPUOperand>(Token);
257     Res->Tok.Data = Str.data();
258     Res->Tok.Length = Str.size();
259     Res->StartLoc = Loc;
260     Res->EndLoc = Loc;
261     return Res;
262   }
263 
CreateReg(unsigned RegNo,SMLoc S,SMLoc E,const MCRegisterInfo * TRI)264   static std::unique_ptr<AMDGPUOperand> CreateReg(unsigned RegNo, SMLoc S,
265                                                   SMLoc E,
266                                                   const MCRegisterInfo *TRI) {
267     auto Op = llvm::make_unique<AMDGPUOperand>(Register);
268     Op->Reg.RegNo = RegNo;
269     Op->Reg.TRI = TRI;
270     Op->Reg.Modifiers = -1;
271     Op->StartLoc = S;
272     Op->EndLoc = E;
273     return Op;
274   }
275 
CreateExpr(const class MCExpr * Expr,SMLoc S)276   static std::unique_ptr<AMDGPUOperand> CreateExpr(const class MCExpr *Expr, SMLoc S) {
277     auto Op = llvm::make_unique<AMDGPUOperand>(Expression);
278     Op->Expr = Expr;
279     Op->StartLoc = S;
280     Op->EndLoc = S;
281     return Op;
282   }
283 
284   bool isDSOffset() const;
285   bool isDSOffset01() const;
286   bool isSWaitCnt() const;
287   bool isMubufOffset() const;
288 };
289 
290 class AMDGPUAsmParser : public MCTargetAsmParser {
291   MCSubtargetInfo &STI;
292   const MCInstrInfo &MII;
293   MCAsmParser &Parser;
294 
295   unsigned ForcedEncodingSize;
296   /// @name Auto-generated Match Functions
297   /// {
298 
299 #define GET_ASSEMBLER_HEADER
300 #include "AMDGPUGenAsmMatcher.inc"
301 
302   /// }
303 
304 public:
AMDGPUAsmParser(MCSubtargetInfo & STI,MCAsmParser & _Parser,const MCInstrInfo & MII,const MCTargetOptions & Options)305   AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
306                const MCInstrInfo &MII,
307                const MCTargetOptions &Options)
308       : MCTargetAsmParser(), STI(STI), MII(MII), Parser(_Parser),
309         ForcedEncodingSize(0){
310 
311     if (!STI.getFeatureBits()) {
312       // Set default features.
313       STI.ToggleFeature("SOUTHERN_ISLANDS");
314     }
315 
316     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
317   }
318 
getForcedEncodingSize() const319   unsigned getForcedEncodingSize() const {
320     return ForcedEncodingSize;
321   }
322 
setForcedEncodingSize(unsigned Size)323   void setForcedEncodingSize(unsigned Size) {
324     ForcedEncodingSize = Size;
325   }
326 
327   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
328   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
329   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
330                                OperandVector &Operands, MCStreamer &Out,
331                                uint64_t &ErrorInfo,
332                                bool MatchingInlineAsm) override;
333   bool ParseDirective(AsmToken DirectiveID) override;
334   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
335   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
336                         SMLoc NameLoc, OperandVector &Operands) override;
337 
338   OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int,
339                                           int64_t Default = 0);
340   OperandMatchResultTy parseIntWithPrefix(const char *Prefix,
341                                           OperandVector &Operands,
342                                           enum AMDGPUOperand::ImmTy ImmTy =
343                                                       AMDGPUOperand::ImmTyNone);
344   OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
345                                      enum AMDGPUOperand::ImmTy ImmTy =
346                                                       AMDGPUOperand::ImmTyNone);
347   OperandMatchResultTy parseOptionalOps(
348                                    const ArrayRef<OptionalOperand> &OptionalOps,
349                                    OperandVector &Operands);
350 
351 
352   void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
353   void cvtDS(MCInst &Inst, const OperandVector &Operands);
354   OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
355   OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
356   OperandMatchResultTy parseDSOffsetOptional(OperandVector &Operands);
357 
358   bool parseCnt(int64_t &IntVal);
359   OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
360   OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
361 
362   void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
363   OperandMatchResultTy parseOffset(OperandVector &Operands);
364   OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands);
365   OperandMatchResultTy parseGLC(OperandVector &Operands);
366   OperandMatchResultTy parseSLC(OperandVector &Operands);
367   OperandMatchResultTy parseTFE(OperandVector &Operands);
368 
369   OperandMatchResultTy parseDMask(OperandVector &Operands);
370   OperandMatchResultTy parseUNorm(OperandVector &Operands);
371   OperandMatchResultTy parseR128(OperandVector &Operands);
372 
373   void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
374   OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
375 };
376 
377 struct OptionalOperand {
378   const char *Name;
379   AMDGPUOperand::ImmTy Type;
380   bool IsBit;
381   int64_t Default;
382   bool (*ConvertResult)(int64_t&);
383 };
384 
385 }
386 
getRegClass(bool IsVgpr,unsigned RegWidth)387 static unsigned getRegClass(bool IsVgpr, unsigned RegWidth) {
388   if (IsVgpr) {
389     switch (RegWidth) {
390       default: llvm_unreachable("Unknown register width");
391       case 1: return AMDGPU::VGPR_32RegClassID;
392       case 2: return AMDGPU::VReg_64RegClassID;
393       case 3: return AMDGPU::VReg_96RegClassID;
394       case 4: return AMDGPU::VReg_128RegClassID;
395       case 8: return AMDGPU::VReg_256RegClassID;
396       case 16: return AMDGPU::VReg_512RegClassID;
397     }
398   }
399 
400   switch (RegWidth) {
401     default: llvm_unreachable("Unknown register width");
402     case 1: return AMDGPU::SGPR_32RegClassID;
403     case 2: return AMDGPU::SGPR_64RegClassID;
404     case 4: return AMDGPU::SReg_128RegClassID;
405     case 8: return AMDGPU::SReg_256RegClassID;
406     case 16: return AMDGPU::SReg_512RegClassID;
407   }
408 }
409 
getRegForName(const StringRef & RegName)410 static unsigned getRegForName(const StringRef &RegName) {
411 
412   return StringSwitch<unsigned>(RegName)
413     .Case("exec", AMDGPU::EXEC)
414     .Case("vcc", AMDGPU::VCC)
415     .Case("flat_scr", AMDGPU::FLAT_SCR)
416     .Case("m0", AMDGPU::M0)
417     .Case("scc", AMDGPU::SCC)
418     .Case("flat_scr_lo", AMDGPU::FLAT_SCR_LO)
419     .Case("flat_scr_hi", AMDGPU::FLAT_SCR_HI)
420     .Case("vcc_lo", AMDGPU::VCC_LO)
421     .Case("vcc_hi", AMDGPU::VCC_HI)
422     .Case("exec_lo", AMDGPU::EXEC_LO)
423     .Case("exec_hi", AMDGPU::EXEC_HI)
424     .Default(0);
425 }
426 
ParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)427 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
428   const AsmToken Tok = Parser.getTok();
429   StartLoc = Tok.getLoc();
430   EndLoc = Tok.getEndLoc();
431   const StringRef &RegName = Tok.getString();
432   RegNo = getRegForName(RegName);
433 
434   if (RegNo) {
435     Parser.Lex();
436     return false;
437   }
438 
439   // Match vgprs and sgprs
440   if (RegName[0] != 's' && RegName[0] != 'v')
441     return true;
442 
443   bool IsVgpr = RegName[0] == 'v';
444   unsigned RegWidth;
445   unsigned RegIndexInClass;
446   if (RegName.size() > 1) {
447     // We have a 32-bit register
448     RegWidth = 1;
449     if (RegName.substr(1).getAsInteger(10, RegIndexInClass))
450       return true;
451     Parser.Lex();
452   } else {
453     // We have a register greater than 32-bits.
454 
455     int64_t RegLo, RegHi;
456     Parser.Lex();
457     if (getLexer().isNot(AsmToken::LBrac))
458       return true;
459 
460     Parser.Lex();
461     if (getParser().parseAbsoluteExpression(RegLo))
462       return true;
463 
464     if (getLexer().isNot(AsmToken::Colon))
465       return true;
466 
467     Parser.Lex();
468     if (getParser().parseAbsoluteExpression(RegHi))
469       return true;
470 
471     if (getLexer().isNot(AsmToken::RBrac))
472       return true;
473 
474     Parser.Lex();
475     RegWidth = (RegHi - RegLo) + 1;
476     if (IsVgpr) {
477       // VGPR registers aren't aligned.
478       RegIndexInClass = RegLo;
479     } else {
480       // SGPR registers are aligned.  Max alignment is 4 dwords.
481       RegIndexInClass = RegLo / std::min(RegWidth, 4u);
482     }
483   }
484 
485   const MCRegisterInfo *TRC = getContext().getRegisterInfo();
486   unsigned RC = getRegClass(IsVgpr, RegWidth);
487   if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs())
488     return true;
489   RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
490   return false;
491 }
492 
checkTargetMatchPredicate(MCInst & Inst)493 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
494 
495   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
496 
497   if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
498       (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)))
499     return Match_InvalidOperand;
500 
501   return Match_Success;
502 }
503 
504 
MatchAndEmitInstruction(SMLoc IDLoc,unsigned & Opcode,OperandVector & Operands,MCStreamer & Out,uint64_t & ErrorInfo,bool MatchingInlineAsm)505 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
506                                               OperandVector &Operands,
507                                               MCStreamer &Out,
508                                               uint64_t &ErrorInfo,
509                                               bool MatchingInlineAsm) {
510   MCInst Inst;
511 
512   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
513     default: break;
514     case Match_Success:
515       Inst.setLoc(IDLoc);
516       Out.EmitInstruction(Inst, STI);
517       return false;
518     case Match_MissingFeature:
519       return Error(IDLoc, "missing feature");
520 
521     case Match_MnemonicFail:
522       return Error(IDLoc, "unrecognized instruction mnemonic");
523 
524     case Match_InvalidOperand: {
525       SMLoc ErrorLoc = IDLoc;
526       if (ErrorInfo != ~0ULL) {
527         if (ErrorInfo >= Operands.size()) {
528           return Error(IDLoc, "too few operands for instruction");
529         }
530 
531         ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
532         if (ErrorLoc == SMLoc())
533           ErrorLoc = IDLoc;
534       }
535       return Error(ErrorLoc, "invalid operand for instruction");
536     }
537   }
538   llvm_unreachable("Implement any new match types added!");
539 }
540 
ParseDirective(AsmToken DirectiveID)541 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
542   return true;
543 }
544 
operandsHaveModifiers(const OperandVector & Operands)545 static bool operandsHaveModifiers(const OperandVector &Operands) {
546 
547   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
548     const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
549     if (Op.isRegWithInputMods())
550       return true;
551     if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod ||
552                        Op.getImmTy() == AMDGPUOperand::ImmTyClamp))
553       return true;
554   }
555   return false;
556 }
557 
558 AMDGPUAsmParser::OperandMatchResultTy
parseOperand(OperandVector & Operands,StringRef Mnemonic)559 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
560 
561   // Try to parse with a custom parser
562   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
563 
564   // If we successfully parsed the operand or if there as an error parsing,
565   // we are done.
566   //
567   // If we are parsing after we reach EndOfStatement then this means we
568   // are appending default values to the Operands list.  This is only done
569   // by custom parser, so we shouldn't continue on to the generic parsing.
570   if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
571       getLexer().is(AsmToken::EndOfStatement))
572     return ResTy;
573 
574   bool Negate = false, Abs = false;
575   if (getLexer().getKind()== AsmToken::Minus) {
576     Parser.Lex();
577     Negate = true;
578   }
579 
580   if (getLexer().getKind() == AsmToken::Pipe) {
581     Parser.Lex();
582     Abs = true;
583   }
584 
585   switch(getLexer().getKind()) {
586     case AsmToken::Integer: {
587       SMLoc S = Parser.getTok().getLoc();
588       int64_t IntVal;
589       if (getParser().parseAbsoluteExpression(IntVal))
590         return MatchOperand_ParseFail;
591       APInt IntVal32(32, IntVal);
592       if (IntVal32.getSExtValue() != IntVal) {
593         Error(S, "invalid immediate: only 32-bit values are legal");
594         return MatchOperand_ParseFail;
595       }
596 
597       IntVal = IntVal32.getSExtValue();
598       if (Negate)
599         IntVal *= -1;
600       Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
601       return MatchOperand_Success;
602     }
603     case AsmToken::Real: {
604       // FIXME: We should emit an error if a double precisions floating-point
605       // value is used.  I'm not sure the best way to detect this.
606       SMLoc S = Parser.getTok().getLoc();
607       int64_t IntVal;
608       if (getParser().parseAbsoluteExpression(IntVal))
609         return MatchOperand_ParseFail;
610 
611       APFloat F((float)BitsToDouble(IntVal));
612       if (Negate)
613         F.changeSign();
614       Operands.push_back(
615           AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S));
616       return MatchOperand_Success;
617     }
618     case AsmToken::Identifier: {
619       SMLoc S, E;
620       unsigned RegNo;
621       if (!ParseRegister(RegNo, S, E)) {
622 
623         bool HasModifiers = operandsHaveModifiers(Operands);
624         unsigned Modifiers = 0;
625 
626         if (Negate)
627           Modifiers |= 0x1;
628 
629         if (Abs) {
630           if (getLexer().getKind() != AsmToken::Pipe)
631             return MatchOperand_ParseFail;
632           Parser.Lex();
633           Modifiers |= 0x2;
634         }
635 
636         if (Modifiers && !HasModifiers) {
637           // We are adding a modifier to src1 or src2 and previous sources
638           // don't have modifiers, so we need to go back and empty modifers
639           // for each previous source.
640           for (unsigned PrevRegIdx = Operands.size() - 1; PrevRegIdx > 1;
641                --PrevRegIdx) {
642 
643             AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]);
644             RegOp.setModifiers(0);
645           }
646         }
647 
648 
649         Operands.push_back(AMDGPUOperand::CreateReg(
650             RegNo, S, E, getContext().getRegisterInfo()));
651 
652         if (HasModifiers || Modifiers) {
653           AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]);
654           RegOp.setModifiers(Modifiers);
655 
656         }
657      }  else {
658       Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),
659                                                     S));
660       Parser.Lex();
661      }
662      return MatchOperand_Success;
663     }
664     default:
665       return MatchOperand_NoMatch;
666   }
667 }
668 
ParseInstruction(ParseInstructionInfo & Info,StringRef Name,SMLoc NameLoc,OperandVector & Operands)669 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
670                                        StringRef Name,
671                                        SMLoc NameLoc, OperandVector &Operands) {
672 
673   // Clear any forced encodings from the previous instruction.
674   setForcedEncodingSize(0);
675 
676   if (Name.endswith("_e64"))
677     setForcedEncodingSize(64);
678   else if (Name.endswith("_e32"))
679     setForcedEncodingSize(32);
680 
681   // Add the instruction mnemonic
682   Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
683 
684   while (!getLexer().is(AsmToken::EndOfStatement)) {
685     AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
686 
687     // Eat the comma or space if there is one.
688     if (getLexer().is(AsmToken::Comma))
689       Parser.Lex();
690 
691     switch (Res) {
692       case MatchOperand_Success: break;
693       case MatchOperand_ParseFail: return Error(getLexer().getLoc(),
694                                                 "failed parsing operand.");
695       case MatchOperand_NoMatch: return Error(getLexer().getLoc(),
696                                               "not a valid operand.");
697     }
698   }
699 
700   // Once we reach end of statement, continue parsing so we can add default
701   // values for optional arguments.
702   AMDGPUAsmParser::OperandMatchResultTy Res;
703   while ((Res = parseOperand(Operands, Name)) != MatchOperand_NoMatch) {
704     if (Res != MatchOperand_Success)
705       return Error(getLexer().getLoc(), "failed parsing operand.");
706   }
707   return false;
708 }
709 
710 //===----------------------------------------------------------------------===//
711 // Utility functions
712 //===----------------------------------------------------------------------===//
713 
714 AMDGPUAsmParser::OperandMatchResultTy
parseIntWithPrefix(const char * Prefix,int64_t & Int,int64_t Default)715 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int,
716                                     int64_t Default) {
717 
718   // We are at the end of the statement, and this is a default argument, so
719   // use a default value.
720   if (getLexer().is(AsmToken::EndOfStatement)) {
721     Int = Default;
722     return MatchOperand_Success;
723   }
724 
725   switch(getLexer().getKind()) {
726     default: return MatchOperand_NoMatch;
727     case AsmToken::Identifier: {
728       StringRef OffsetName = Parser.getTok().getString();
729       if (!OffsetName.equals(Prefix))
730         return MatchOperand_NoMatch;
731 
732       Parser.Lex();
733       if (getLexer().isNot(AsmToken::Colon))
734         return MatchOperand_ParseFail;
735 
736       Parser.Lex();
737       if (getLexer().isNot(AsmToken::Integer))
738         return MatchOperand_ParseFail;
739 
740       if (getParser().parseAbsoluteExpression(Int))
741         return MatchOperand_ParseFail;
742       break;
743     }
744   }
745   return MatchOperand_Success;
746 }
747 
748 AMDGPUAsmParser::OperandMatchResultTy
parseIntWithPrefix(const char * Prefix,OperandVector & Operands,enum AMDGPUOperand::ImmTy ImmTy)749 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
750                                     enum AMDGPUOperand::ImmTy ImmTy) {
751 
752   SMLoc S = Parser.getTok().getLoc();
753   int64_t Offset = 0;
754 
755   AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Offset);
756   if (Res != MatchOperand_Success)
757     return Res;
758 
759   Operands.push_back(AMDGPUOperand::CreateImm(Offset, S, ImmTy));
760   return MatchOperand_Success;
761 }
762 
763 AMDGPUAsmParser::OperandMatchResultTy
parseNamedBit(const char * Name,OperandVector & Operands,enum AMDGPUOperand::ImmTy ImmTy)764 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
765                                enum AMDGPUOperand::ImmTy ImmTy) {
766   int64_t Bit = 0;
767   SMLoc S = Parser.getTok().getLoc();
768 
769   // We are at the end of the statement, and this is a default argument, so
770   // use a default value.
771   if (getLexer().isNot(AsmToken::EndOfStatement)) {
772     switch(getLexer().getKind()) {
773       case AsmToken::Identifier: {
774         StringRef Tok = Parser.getTok().getString();
775         if (Tok == Name) {
776           Bit = 1;
777           Parser.Lex();
778         } else if (Tok.startswith("no") && Tok.endswith(Name)) {
779           Bit = 0;
780           Parser.Lex();
781         } else {
782           return MatchOperand_NoMatch;
783         }
784         break;
785       }
786       default:
787         return MatchOperand_NoMatch;
788     }
789   }
790 
791   Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));
792   return MatchOperand_Success;
793 }
794 
operandsHasOptionalOp(const OperandVector & Operands,const OptionalOperand & OOp)795 static bool operandsHasOptionalOp(const OperandVector &Operands,
796                                   const OptionalOperand &OOp) {
797   for (unsigned i = 0; i < Operands.size(); i++) {
798     const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]);
799     if ((ParsedOp.isImm() && ParsedOp.getImmTy() == OOp.Type) ||
800         (ParsedOp.isToken() && ParsedOp.getToken() == OOp.Name))
801       return true;
802 
803   }
804   return false;
805 }
806 
807 AMDGPUAsmParser::OperandMatchResultTy
parseOptionalOps(const ArrayRef<OptionalOperand> & OptionalOps,OperandVector & Operands)808 AMDGPUAsmParser::parseOptionalOps(const ArrayRef<OptionalOperand> &OptionalOps,
809                                    OperandVector &Operands) {
810   SMLoc S = Parser.getTok().getLoc();
811   for (const OptionalOperand &Op : OptionalOps) {
812     if (operandsHasOptionalOp(Operands, Op))
813       continue;
814     AMDGPUAsmParser::OperandMatchResultTy Res;
815     int64_t Value;
816     if (Op.IsBit) {
817       Res = parseNamedBit(Op.Name, Operands, Op.Type);
818       if (Res == MatchOperand_NoMatch)
819         continue;
820       return Res;
821     }
822 
823     Res = parseIntWithPrefix(Op.Name, Value, Op.Default);
824 
825     if (Res == MatchOperand_NoMatch)
826       continue;
827 
828     if (Res != MatchOperand_Success)
829       return Res;
830 
831     if (Op.ConvertResult && !Op.ConvertResult(Value)) {
832       return MatchOperand_ParseFail;
833     }
834 
835     Operands.push_back(AMDGPUOperand::CreateImm(Value, S, Op.Type));
836     return MatchOperand_Success;
837   }
838   return MatchOperand_NoMatch;
839 }
840 
841 //===----------------------------------------------------------------------===//
842 // ds
843 //===----------------------------------------------------------------------===//
844 
845 static const OptionalOperand DSOptionalOps [] = {
846   {"offset",  AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
847   {"gds",     AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
848 };
849 
850 static const OptionalOperand DSOptionalOpsOff01 [] = {
851   {"offset0", AMDGPUOperand::ImmTyDSOffset0, false, 0, nullptr},
852   {"offset1", AMDGPUOperand::ImmTyDSOffset1, false, 0, nullptr},
853   {"gds",     AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
854 };
855 
856 AMDGPUAsmParser::OperandMatchResultTy
parseDSOptionalOps(OperandVector & Operands)857 AMDGPUAsmParser::parseDSOptionalOps(OperandVector &Operands) {
858   return parseOptionalOps(DSOptionalOps, Operands);
859 }
860 AMDGPUAsmParser::OperandMatchResultTy
parseDSOff01OptionalOps(OperandVector & Operands)861 AMDGPUAsmParser::parseDSOff01OptionalOps(OperandVector &Operands) {
862   return parseOptionalOps(DSOptionalOpsOff01, Operands);
863 }
864 
865 AMDGPUAsmParser::OperandMatchResultTy
parseDSOffsetOptional(OperandVector & Operands)866 AMDGPUAsmParser::parseDSOffsetOptional(OperandVector &Operands) {
867   SMLoc S = Parser.getTok().getLoc();
868   AMDGPUAsmParser::OperandMatchResultTy Res =
869     parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);
870   if (Res == MatchOperand_NoMatch) {
871     Operands.push_back(AMDGPUOperand::CreateImm(0, S,
872                        AMDGPUOperand::ImmTyOffset));
873     Res = MatchOperand_Success;
874   }
875   return Res;
876 }
877 
isDSOffset() const878 bool AMDGPUOperand::isDSOffset() const {
879   return isImm() && isUInt<16>(getImm());
880 }
881 
isDSOffset01() const882 bool AMDGPUOperand::isDSOffset01() const {
883   return isImm() && isUInt<8>(getImm());
884 }
885 
cvtDSOffset01(MCInst & Inst,const OperandVector & Operands)886 void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
887                                     const OperandVector &Operands) {
888 
889   std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
890 
891   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
892     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
893 
894     // Add the register arguments
895     if (Op.isReg()) {
896       Op.addRegOperands(Inst, 1);
897       continue;
898     }
899 
900     // Handle optional arguments
901     OptionalIdx[Op.getImmTy()] = i;
902   }
903 
904   unsigned Offset0Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset0];
905   unsigned Offset1Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset1];
906   unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
907 
908   ((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0
909   ((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1
910   ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
911   Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
912 }
913 
cvtDS(MCInst & Inst,const OperandVector & Operands)914 void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
915 
916   std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
917   bool GDSOnly = false;
918 
919   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
920     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
921 
922     // Add the register arguments
923     if (Op.isReg()) {
924       Op.addRegOperands(Inst, 1);
925       continue;
926     }
927 
928     if (Op.isToken() && Op.getToken() == "gds") {
929       GDSOnly = true;
930       continue;
931     }
932 
933     // Handle optional arguments
934     OptionalIdx[Op.getImmTy()] = i;
935   }
936 
937   unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset];
938   ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1); // offset
939 
940   if (!GDSOnly) {
941     unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
942     ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
943   }
944   Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
945 }
946 
947 
948 //===----------------------------------------------------------------------===//
949 // s_waitcnt
950 //===----------------------------------------------------------------------===//
951 
parseCnt(int64_t & IntVal)952 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
953   StringRef CntName = Parser.getTok().getString();
954   int64_t CntVal;
955 
956   Parser.Lex();
957   if (getLexer().isNot(AsmToken::LParen))
958     return true;
959 
960   Parser.Lex();
961   if (getLexer().isNot(AsmToken::Integer))
962     return true;
963 
964   if (getParser().parseAbsoluteExpression(CntVal))
965     return true;
966 
967   if (getLexer().isNot(AsmToken::RParen))
968     return true;
969 
970   Parser.Lex();
971   if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
972     Parser.Lex();
973 
974   int CntShift;
975   int CntMask;
976 
977   if (CntName == "vmcnt") {
978     CntMask = 0xf;
979     CntShift = 0;
980   } else if (CntName == "expcnt") {
981     CntMask = 0x7;
982     CntShift = 4;
983   } else if (CntName == "lgkmcnt") {
984     CntMask = 0x7;
985     CntShift = 8;
986   } else {
987     return true;
988   }
989 
990   IntVal &= ~(CntMask << CntShift);
991   IntVal |= (CntVal << CntShift);
992   return false;
993 }
994 
995 AMDGPUAsmParser::OperandMatchResultTy
parseSWaitCntOps(OperandVector & Operands)996 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
997   // Disable all counters by default.
998   // vmcnt   [3:0]
999   // expcnt  [6:4]
1000   // lgkmcnt [10:8]
1001   int64_t CntVal = 0x77f;
1002   SMLoc S = Parser.getTok().getLoc();
1003 
1004   switch(getLexer().getKind()) {
1005     default: return MatchOperand_ParseFail;
1006     case AsmToken::Integer:
1007       // The operand can be an integer value.
1008       if (getParser().parseAbsoluteExpression(CntVal))
1009         return MatchOperand_ParseFail;
1010       break;
1011 
1012     case AsmToken::Identifier:
1013       do {
1014         if (parseCnt(CntVal))
1015           return MatchOperand_ParseFail;
1016       } while(getLexer().isNot(AsmToken::EndOfStatement));
1017       break;
1018   }
1019   Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S));
1020   return MatchOperand_Success;
1021 }
1022 
isSWaitCnt() const1023 bool AMDGPUOperand::isSWaitCnt() const {
1024   return isImm();
1025 }
1026 
1027 //===----------------------------------------------------------------------===//
1028 // sopp branch targets
1029 //===----------------------------------------------------------------------===//
1030 
1031 AMDGPUAsmParser::OperandMatchResultTy
parseSOppBrTarget(OperandVector & Operands)1032 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
1033   SMLoc S = Parser.getTok().getLoc();
1034 
1035   switch (getLexer().getKind()) {
1036     default: return MatchOperand_ParseFail;
1037     case AsmToken::Integer: {
1038       int64_t Imm;
1039       if (getParser().parseAbsoluteExpression(Imm))
1040         return MatchOperand_ParseFail;
1041       Operands.push_back(AMDGPUOperand::CreateImm(Imm, S));
1042       return MatchOperand_Success;
1043     }
1044 
1045     case AsmToken::Identifier:
1046       Operands.push_back(AMDGPUOperand::CreateExpr(
1047           MCSymbolRefExpr::Create(getContext().GetOrCreateSymbol(
1048                                   Parser.getTok().getString()), getContext()), S));
1049       Parser.Lex();
1050       return MatchOperand_Success;
1051   }
1052 }
1053 
1054 //===----------------------------------------------------------------------===//
1055 // mubuf
1056 //===----------------------------------------------------------------------===//
1057 
1058 static const OptionalOperand MubufOptionalOps [] = {
1059   {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
1060   {"glc",    AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
1061   {"slc",    AMDGPUOperand::ImmTySLC, true, 0, nullptr},
1062   {"tfe",    AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
1063 };
1064 
1065 AMDGPUAsmParser::OperandMatchResultTy
parseMubufOptionalOps(OperandVector & Operands)1066 AMDGPUAsmParser::parseMubufOptionalOps(OperandVector &Operands) {
1067   return parseOptionalOps(MubufOptionalOps, Operands);
1068 }
1069 
1070 AMDGPUAsmParser::OperandMatchResultTy
parseOffset(OperandVector & Operands)1071 AMDGPUAsmParser::parseOffset(OperandVector &Operands) {
1072   return parseIntWithPrefix("offset", Operands);
1073 }
1074 
1075 AMDGPUAsmParser::OperandMatchResultTy
parseGLC(OperandVector & Operands)1076 AMDGPUAsmParser::parseGLC(OperandVector &Operands) {
1077   return parseNamedBit("glc", Operands);
1078 }
1079 
1080 AMDGPUAsmParser::OperandMatchResultTy
parseSLC(OperandVector & Operands)1081 AMDGPUAsmParser::parseSLC(OperandVector &Operands) {
1082   return parseNamedBit("slc", Operands);
1083 }
1084 
1085 AMDGPUAsmParser::OperandMatchResultTy
parseTFE(OperandVector & Operands)1086 AMDGPUAsmParser::parseTFE(OperandVector &Operands) {
1087   return parseNamedBit("tfe", Operands);
1088 }
1089 
isMubufOffset() const1090 bool AMDGPUOperand::isMubufOffset() const {
1091   return isImm() && isUInt<12>(getImm());
1092 }
1093 
cvtMubuf(MCInst & Inst,const OperandVector & Operands)1094 void AMDGPUAsmParser::cvtMubuf(MCInst &Inst,
1095                                const OperandVector &Operands) {
1096   std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1097 
1098   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1099     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1100 
1101     // Add the register arguments
1102     if (Op.isReg()) {
1103       Op.addRegOperands(Inst, 1);
1104       continue;
1105     }
1106 
1107     // Handle the case where soffset is an immediate
1108     if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
1109       Op.addImmOperands(Inst, 1);
1110       continue;
1111     }
1112 
1113     // Handle tokens like 'offen' which are sometimes hard-coded into the
1114     // asm string.  There are no MCInst operands for these.
1115     if (Op.isToken()) {
1116       continue;
1117     }
1118     assert(Op.isImm());
1119 
1120     // Handle optional arguments
1121     OptionalIdx[Op.getImmTy()] = i;
1122   }
1123 
1124   assert(OptionalIdx.size() == 4);
1125 
1126   unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset];
1127   unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC];
1128   unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC];
1129   unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE];
1130 
1131   ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1);
1132   ((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);
1133   ((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);
1134   ((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);
1135 }
1136 
1137 //===----------------------------------------------------------------------===//
1138 // mimg
1139 //===----------------------------------------------------------------------===//
1140 
1141 AMDGPUAsmParser::OperandMatchResultTy
parseDMask(OperandVector & Operands)1142 AMDGPUAsmParser::parseDMask(OperandVector &Operands) {
1143   return parseIntWithPrefix("dmask", Operands);
1144 }
1145 
1146 AMDGPUAsmParser::OperandMatchResultTy
parseUNorm(OperandVector & Operands)1147 AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {
1148   return parseNamedBit("unorm", Operands);
1149 }
1150 
1151 AMDGPUAsmParser::OperandMatchResultTy
parseR128(OperandVector & Operands)1152 AMDGPUAsmParser::parseR128(OperandVector &Operands) {
1153   return parseNamedBit("r128", Operands);
1154 }
1155 
1156 //===----------------------------------------------------------------------===//
1157 // vop3
1158 //===----------------------------------------------------------------------===//
1159 
ConvertOmodMul(int64_t & Mul)1160 static bool ConvertOmodMul(int64_t &Mul) {
1161   if (Mul != 1 && Mul != 2 && Mul != 4)
1162     return false;
1163 
1164   Mul >>= 1;
1165   return true;
1166 }
1167 
ConvertOmodDiv(int64_t & Div)1168 static bool ConvertOmodDiv(int64_t &Div) {
1169   if (Div == 1) {
1170     Div = 0;
1171     return true;
1172   }
1173 
1174   if (Div == 2) {
1175     Div = 3;
1176     return true;
1177   }
1178 
1179   return false;
1180 }
1181 
1182 static const OptionalOperand VOP3OptionalOps [] = {
1183   {"clamp", AMDGPUOperand::ImmTyClamp, true, 0, nullptr},
1184   {"mul",   AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodMul},
1185   {"div",   AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodDiv},
1186 };
1187 
isVOP3(OperandVector & Operands)1188 static bool isVOP3(OperandVector &Operands) {
1189   if (operandsHaveModifiers(Operands))
1190     return true;
1191 
1192   AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);
1193 
1194   if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
1195     return true;
1196 
1197   if (Operands.size() >= 5)
1198     return true;
1199 
1200   if (Operands.size() > 3) {
1201     AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]);
1202     if (Src1Op.getReg() && (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) ||
1203                             Src1Op.isRegClass(AMDGPU::SReg_64RegClassID)))
1204       return true;
1205   }
1206   return false;
1207 }
1208 
1209 AMDGPUAsmParser::OperandMatchResultTy
parseVOP3OptionalOps(OperandVector & Operands)1210 AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) {
1211 
1212   // The value returned by this function may change after parsing
1213   // an operand so store the original value here.
1214   bool HasModifiers = operandsHaveModifiers(Operands);
1215 
1216   bool IsVOP3 = isVOP3(Operands);
1217   if (HasModifiers || IsVOP3 ||
1218       getLexer().isNot(AsmToken::EndOfStatement) ||
1219       getForcedEncodingSize() == 64) {
1220 
1221     AMDGPUAsmParser::OperandMatchResultTy Res =
1222         parseOptionalOps(VOP3OptionalOps, Operands);
1223 
1224     if (!HasModifiers && Res == MatchOperand_Success) {
1225       // We have added a modifier operation, so we need to make sure all
1226       // previous register operands have modifiers
1227       for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
1228         AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
1229         if (Op.isReg())
1230           Op.setModifiers(0);
1231       }
1232     }
1233     return Res;
1234   }
1235   return MatchOperand_NoMatch;
1236 }
1237 
cvtVOP3(MCInst & Inst,const OperandVector & Operands)1238 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
1239   ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1);
1240   unsigned i = 2;
1241 
1242   std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1243 
1244   if (operandsHaveModifiers(Operands)) {
1245     for (unsigned e = Operands.size(); i != e; ++i) {
1246       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1247 
1248       if (Op.isRegWithInputMods()) {
1249         ((AMDGPUOperand &)*Operands[i]).addRegWithInputModsOperands(Inst, 2);
1250         continue;
1251       }
1252       OptionalIdx[Op.getImmTy()] = i;
1253     }
1254 
1255     unsigned ClampIdx = OptionalIdx[AMDGPUOperand::ImmTyClamp];
1256     unsigned OModIdx = OptionalIdx[AMDGPUOperand::ImmTyOMod];
1257 
1258     ((AMDGPUOperand &)*Operands[ClampIdx]).addImmOperands(Inst, 1);
1259     ((AMDGPUOperand &)*Operands[OModIdx]).addImmOperands(Inst, 1);
1260   } else {
1261     for (unsigned e = Operands.size(); i != e; ++i)
1262       ((AMDGPUOperand &)*Operands[i]).addRegOrImmOperands(Inst, 1);
1263   }
1264 }
1265 
1266 /// Force static initialization.
LLVMInitializeR600AsmParser()1267 extern "C" void LLVMInitializeR600AsmParser() {
1268   RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget);
1269   RegisterMCAsmParser<AMDGPUAsmParser> B(TheGCNTarget);
1270 }
1271 
1272 #define GET_REGISTER_MATCHER
1273 #define GET_MATCHER_IMPLEMENTATION
1274 #include "AMDGPUGenAsmMatcher.inc"
1275 
1276