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Searched refs:LOAD (Results 1 – 25 of 85) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Dvector-promotion.ll6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
14 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
15 ; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
16 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
34 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
35 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
D2012-08-09-neon-extload.ll21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
36 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
[all …]
/external/valgrind/memcheck/tests/
Dcond_ld.stderr.exp-64bit-non-arm3 LOAD CASE 0
8 LOAD CASE 1
13 LOAD CASE 2
18 LOAD CASE 3
23 LOAD CASE 4
40 LOAD CASE 5
57 LOAD CASE 6
74 LOAD CASE 7
91 LOAD CASE 8
102 LOAD CASE 9
[all …]
Dcond_ld.stderr.exp-arm3 LOAD CASE 0
8 LOAD CASE 1
13 LOAD CASE 2
18 LOAD CASE 3
23 LOAD CASE 4
40 LOAD CASE 5
57 LOAD CASE 6
74 LOAD CASE 7
91 LOAD CASE 8
102 LOAD CASE 9
[all …]
Dcond_ld.stderr.exp-32bit-non-arm3 LOAD CASE 0
8 LOAD CASE 1
13 LOAD CASE 2
18 LOAD CASE 3
23 LOAD CASE 4
40 LOAD CASE 5
57 LOAD CASE 6
74 LOAD CASE 7
91 LOAD CASE 8
102 LOAD CASE 9
[all …]
/external/llvm/test/CodeGen/R600/
Dtrunc-cmp-constant.ll5 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
6 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
21 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
22 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
47 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
48 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
59 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
60 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
83 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
84 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
[all …]
Dtrunc-store-i1.ll6 ; SI: s_load_dword [[LOAD:s[0-9]+]],
7 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
25 ; SI: s_load_dword [[LOAD:s[0-9]+]],
26 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
/external/llvm/test/tools/llvm-objdump/X86/
Dmacho-private-headers.test5 // RUN: | FileCheck %s -check-prefix=LOAD
362 LOAD: Load command 10
363 LOAD: cmd LC_LOAD_DYLIB
364 LOAD: cmdsize 48
365 LOAD: name /usr/lib/foo1.dylib (offset 24)
366 LOAD: current version 0.0.0
367 LOAD: compatibility version 0.0.0
368 LOAD: Load command 11
369 LOAD: cmd LC_LOAD_WEAK_DYLIB
370 LOAD: cmdsize 48
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/external/boringssl/src/crypto/chacha/
Dchacha_vec.c49 #define LOAD(m) ({ \ macro
83 #define LOAD(m) (vec) _mm_loadu_si128((__m128i *)(m)) macro
140 STORE(op + d + 0, LOAD(in + d + 0) ^ REVV_BE(v0)); \
141 STORE(op + d + 4, LOAD(in + d + 4) ^ REVV_BE(v1)); \
142 STORE(op + d + 8, LOAD(in + d + 8) ^ REVV_BE(v2)); \
143 STORE(op + d +12, LOAD(in + d +12) ^ REVV_BE(v3));
173 s1 = LOAD(&((vec*)kp)[0]); in CRYPTO_chacha_20_neon()
174 s2 = LOAD(&((vec*)kp)[1]); in CRYPTO_chacha_20_neon()
303 STORE(op + 0, LOAD(ip + 0) ^ REVV_BE(v0 + s0)); in CRYPTO_chacha_20_neon()
306 STORE(op + 4, LOAD(ip + 4) ^ REVV_BE(v1 + s1)); in CRYPTO_chacha_20_neon()
[all …]
/external/v8/src/compiler/
Dmachine-operator.cc154 #define LOAD(Type) \ macro
162 MACHINE_TYPE_LIST(LOAD)
163 #undef LOAD
207 #define LOAD(Type) \ in PURE_OP_LIST() macro
210 MACHINE_TYPE_LIST(LOAD) in PURE_OP_LIST()
211 #undef LOAD in PURE_OP_LIST()
/external/llvm/lib/Target/SystemZ/
DSystemZPatterns.td40 // with LOAD, OPERATOR and STORE being the read, modify and write
58 // The inserted operand is loaded using LOAD from an address of mode MODE.
98 // condition is false. Record that they are equivalent to a LOAD/select/STORE
115 // Try to use MVC instruction INSN for a load of type LOAD followed by a store
117 // LENGTH is the number of bytes loaded by LOAD.
125 // The other operand is a load of type LOAD, which accesses LENGTH bytes.
135 // LOAD/VT/LENGTH combination.
148 // Record that INSN is a LOAD AND TEST that can be used to compare
DREADME.txt32 The tuning of the choice between LOAD ADDRESS (LA) and addition in
55 We could use the generic floating-point forms of LOAD COMPLEMENT,
56 LOAD NEGATIVE and LOAD POSITIVE in cases where we don't need the
88 We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
/external/llvm/test/Transforms/InstCombine/
Dextractvalue.ll44 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32, i32* [[GEP]]
48 ; CHECK: call {{.*}}(i32 [[LOAD]])
50 ; CHECK: ret i32 [[LOAD]]
72 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32, i32* [[GEP]]
73 ; CHECK-NEXT: ret i32 [[LOAD]]
Dstruct-assign-tbaa.ll13 ; CHECK: %[[LOAD:.*]] = load i32, i32* %{{.*}}, align 4, !tbaa !0
14 ; CHECK: store i32 %[[LOAD:.*]], i32* %{{.*}}, align 4, !tbaa !0
/external/llvm/test/Transforms/SimplifyCFG/
Dno_speculative_loads_with_tsan.ll18 ; CHECK: %[[LOAD:[^ ]*]] = load
19 ; CHECK: select{{.*}}[[LOAD]]
/external/llvm/test/Object/
Dobjdump-private-headers.test9 ELF-i386: LOAD off 0x00000000 vaddr 0x08048000 paddr 0x08048000 align 2**12
15 ELF-x86-64: LOAD off 0x0000000000000000 vaddr 0x0000000000400000 paddr 0x0000000000400000 al…
/external/llvm/test/Transforms/JumpThreading/
Dthread-loads.ll88 ; CHECK: %[[LOAD:.*]] = load i32*, i32**
89 ; CHECK: %[[CAST:.*]] = bitcast i32* %[[LOAD]] to i8*
/external/elfutils/src/libebl/
Deblsegmenttypename.c54 PTYPE (LOAD),
/external/libavc/encoder/arm/
Dime_distortion_metrics_a9q.s589 vld1.8 {d2, d3}, [r5], r10 @ y top LOAD
590 vld1.8 {d4, d5}, [r7], r10 @ xy top LOAD
591 vld1.8 {d6, d7}, [r8], r10 @ xy top-left LOAD
595 vld1.8 {d8, d9}, [r1], r10 @ x LOAD
598 vld1.8 {d10, d11}, [r4], r10 @ x left LOAD
602 vld1.8 {d2, d3}, [r2], r10 @ y LOAD
605 vld1.8 {d4, d5}, [r3], r10 @ xy LOAD
609 vld1.8 {d6, d7}, [r6], r10 @ xy left LOAD
624 vld1.8 {d8, d9}, [r1], r10 @ x LOAD
627 vld1.8 {d10, d11}, [r4], r10 @ x left LOAD
[all …]
/external/freetype/src/gzip/
Dinfcodes.c98 LOAD in inflate_codes()
109 LOAD in inflate_codes()
Dinfutil.h85 #define LOAD {LOADIN LOADOUT} macro
Dinfblock.c133 LOAD in inflate_blocks()
344 LOAD in inflate_blocks()
/external/llvm/test/Bitcode/
Dinvalid.test18 RUN: FileCheck --check-prefix=MISMATCHED-EXPLICIT-LOAD %s
30 MISMATCHED-EXPLICIT-LOAD: Explicit load type does not match pointee type of pointer operand
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp53 setOperationAction(ISD::LOAD, MVT::i32, Custom); in SITargetLowering()
54 setOperationAction(ISD::LOAD, MVT::i64, Custom); in SITargetLowering()
266 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
/external/llvm/test/Transforms/LoopVectorize/
Dinduction.ll144 ; CHECK: %[[LOAD:.*]] = load i8
145 ; CHECK: %[[VAL:.*]] = zext i8 %[[LOAD]] to i32

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