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Searched refs:Lanes (Results 1 – 4 of 4) sorted by relevance

/external/llvm/include/llvm/IR/
DIntrinsicsAArch64.td160 // Vector Add Across Lanes
165 // Vector Long Add Across Lanes
256 // Vector Max Across Lanes
272 // Vector Min Across Lanes
/external/llvm/lib/CodeGen/
DRegisterCoalescer.cpp1875 unsigned Lanes = SubRangeJoin ? 1 : TRI->getSubRegIndexLaneMask(SubIdx); in analyzeValue() local
1876 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
2177 unsigned Lanes) const { in usesLanes()
2185 if (Lanes & TRI->getSubRegIndexLaneMask( in usesLanes()
/external/valgrind/
DREADME.aarch64236 math_MINMAXV: use real Iop_Cat{Odd,Even}Lanes ops rather than
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp9231 SmallVector<int, 4> Lanes; in lowerVectorShuffleByMerging128BitLanes() local
9232 Lanes.resize(NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes()
9241 if (Lanes[j] < 0) { in lowerVectorShuffleByMerging128BitLanes()
9243 Lanes[j] = Mask[i] / LaneSize; in lowerVectorShuffleByMerging128BitLanes()
9244 } else if (Lanes[j] != Mask[i] / LaneSize) { in lowerVectorShuffleByMerging128BitLanes()
9265 if (Lanes[i] >= 0) { in lowerVectorShuffleByMerging128BitLanes()
9266 LaneMask[2 * i + 0] = 2*Lanes[i] + 0; in lowerVectorShuffleByMerging128BitLanes()
9267 LaneMask[2 * i + 1] = 2*Lanes[i] + 1; in lowerVectorShuffleByMerging128BitLanes()