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Searched refs:Logical (Results 1 – 25 of 65) sorted by relevance

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/external/llvm/test/MC/Disassembler/Hexagon/
Dcr.txt10 # Logical reductions on predicates
44 # Logical operations on predicates
Dxtype_alu.txt68 # Logical doublewords
82 # Logical-logical doublewords
86 # Logical-logical words
/external/e2fsprogs/tests/f_extent_interior_start_lblk/
Dexpect.13 Logical start 0 does not match logical start 2 at next level. Fix? yes
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV4.td194 // Logical xor with xor accumulation
228 // ALU32 / ALU / Logical Operations.
259 // CR / Logical Operations On Predicates.
286 // XTYPE / ALU / Logical-logical Words.
/external/mesa3d/src/gallium/docs/source/cso/
Dblend.rst21 Logical Operations
24 Logical operations, also known as logicops, lops, or rops, are supported.
/external/llvm/test/CodeGen/SystemZ/
Dfp-conv-12.ll6 ; they were added in z196 as the Convert to Logical family of instructions.
Dfp-conv-10.ll6 ; they were added in z196 as the Convert to Logical family of instructions.
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.jdt.debug_3.6.1.v20100715_r361/
Dplugin.properties28 javaLogicalStructures= Java Logical Structures
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dcr.ll19 ; Logical reductions on predicates
35 ; Logical operations on predicates
Dalu32_alu.ll26 ; Logical operations
/external/llvm/test/MC/Mips/
Dmips-alu-instructions.s5 # Logical instructions
Dmips64-alu-instructions.s5 # Logical instructions
Dmicromips-alu-instructions.s6 # Arithmetic and Logical Instructions
/external/llvm/test/Transforms/InstCombine/
Dpr17827.ll64 ; Logical shift right allows a return true because the 'and' guarantees no bits are set.
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt4 # 5.4.2 Logical (immediate)
46 # 5.5.3 Logical (shifted register)
/external/v8/src/arm64/
Dassembler-arm64.cc1181 Logical(rd, rn, operand, AND); in and_()
1188 Logical(rd, rn, operand, ANDS); in ands()
1201 Logical(rd, rn, operand, BIC); in bic()
1208 Logical(rd, rn, operand, BICS); in bics()
1215 Logical(rd, rn, operand, ORR); in orr()
1222 Logical(rd, rn, operand, ORN); in orn()
1229 Logical(rd, rn, operand, EOR); in eor()
1236 Logical(rd, rn, operand, EON); in eon()
2257 void Assembler::Logical(const Register& rd, in Logical() function in v8::internal::Assembler
/external/llvm/test/CodeGen/X86/
Davx2-vector-shifts.ll3 ; AVX2 Logical Shift Left
167 ; SSE Logical Shift Right
Dsse2-vector-shifts.ll3 ; SSE2 Logical Shift Left
157 ; SSE Logical Shift Right
Davx-shift.ll41 ;;; Logical Shift right
Davx2-shift.ll95 ;;; Logical Shift right
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s5 ; 5.4.2 Logical (immediate)
47 ; 5.5.3 Logical (shifted register)
/external/llvm/include/llvm/IR/
DInstruction.def121 // Logical operators (integer operands)
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.cc769 Logical(temp, rn, imm_operand, op); in LogicalMacro()
772 Logical(rd, rn, imm_operand, op); in LogicalMacro()
787 Logical(rd, rn, Operand(temp), op); in LogicalMacro()
791 Logical(rd, rn, operand, op); in LogicalMacro()
Dassembler-a64.cc959 Logical(rd, rn, operand, AND); in and_()
966 Logical(rd, rn, operand, ANDS); in ands()
979 Logical(rd, rn, operand, BIC); in bic()
986 Logical(rd, rn, operand, BICS); in bics()
993 Logical(rd, rn, operand, ORR); in orr()
1000 Logical(rd, rn, operand, ORN); in orn()
1007 Logical(rd, rn, operand, EOR); in eor()
1014 Logical(rd, rn, operand, EON); in eon()
4640 void Assembler::Logical(const Register& rd, in Logical() function in vixl::Assembler
/external/llvm/docs/tutorial/
DLangImpl6.rst55 # Logical unary not.
457 # Logical unary not.

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