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Searched refs:Lowering (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Target/R600/
DAMDGPUISelDAGToDAG.cpp539 const SITargetLowering& Lowering = in Select() local
541 Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
984 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
987 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1013 const SITargetLowering& Lowering = in SelectMUBUFScratch() local
1018 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass, in SelectMUBUFScratch()
1037 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0); in SelectMUBUFScratch()
1077 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
1080 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
1295 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
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DEvergreenInstructions.td582 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
/external/llvm/lib/LTO/
DLTOCodeGenerator.cpp448 const TargetLowering *Lowering = in accumulateAndSortLibcalls() local
451 if (Lowering && TLSet.insert(Lowering).second) in accumulateAndSortLibcalls()
457 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in accumulateAndSortLibcalls()
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll211 ; Lowering to build vector was breaking the single use property of the load of
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2566 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering, in EnsureStackAlignment() argument
2568 unsigned TargetAlign = Lowering->getStackAlignment(); in EnsureStackAlignment()