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Searched refs:M0Reg (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Target/R600/
DSILoadStoreOptimizer.cpp216 const MachineOperand *M0Reg = TII->getNamedOperand(*I, AMDGPU::OpName::m0); in mergeRead2Pair() local
257 .addOperand(*M0Reg) // M0 in mergeRead2Pair()
276 LiveInterval &M0RegLI = LIS->getInterval(M0Reg->getReg()); in mergeRead2Pair()
303 const MachineOperand *M0Reg = TII->getNamedOperand(*I, AMDGPU::OpName::m0); in mergeWrite2Pair() local
342 .addOperand(*M0Reg) // m0 in mergeWrite2Pair()
348 M0Reg->getReg()}; in mergeWrite2Pair()
DSIRegisterInfo.td185 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
189 (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
DSIInstrInfo.td1719 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1733 gds01:$gds, M0Reg:$m0),
1747 M0Reg:$m0),
1762 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds, M0Reg:$m0),
1777 M0Reg:$m0),
1805 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1812 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1826 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1841 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset, M0Reg:$m0),
1854 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
[all …]
DSIInstructions.td492 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16",
493 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
1442 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1449 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1457 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstructions.td569 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
578 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
590 (ins i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),