Home
last modified time | relevance | path

Searched refs:MCID (Results 1 – 25 of 53) sorted by relevance

123

/external/llvm/include/llvm/MC/
DMCInstrDesc.h100 namespace MCID {
214 return Flags & (1 << MCID::Variadic); in isVariadic()
220 return Flags & (1 << MCID::HasOptionalDef); in hasOptionalDef()
227 return Flags & (1 << MCID::Pseudo); in isPseudo()
232 return Flags & (1 << MCID::Return); in isReturn()
237 return Flags & (1 << MCID::Call); in isCall()
244 return Flags & (1 << MCID::Barrier); in isBarrier()
254 return Flags & (1 << MCID::Terminator); in isTerminator()
262 return Flags & (1 << MCID::Branch); in isBranch()
268 return Flags & (1 << MCID::IndirectBranch); in isIndirectBranch()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h71 const MCInstrDesc *MCID; // Instruction descriptor.
113 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
272 const MCInstrDesc &getDesc() const { return *MCID; }
276 int getOpcode() const { return MCID->Opcode; }
390 return hasProperty(MCID::Variadic, Type);
396 return hasProperty(MCID::HasOptionalDef, Type);
403 return hasProperty(MCID::Pseudo, Type);
407 return hasProperty(MCID::Return, Type);
411 return hasProperty(MCID::Call, Type);
418 return hasProperty(MCID::Barrier, Type);
[all …]
DMachineInstrBuilder.h237 const MCInstrDesc &MCID) { in BuildMI() argument
238 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); in BuildMI()
246 const MCInstrDesc &MCID, in BuildMI() argument
248 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) in BuildMI()
259 const MCInstrDesc &MCID, in BuildMI() argument
262 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
270 const MCInstrDesc &MCID, in BuildMI() argument
273 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
281 const MCInstrDesc &MCID, in BuildMI() argument
285 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore() local
32 if (!MCID) in isLoadAfterStore()
35 if (!MCID->mayLoad()) in isLoadAfterStore()
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet() local
58 if (!MCID) in isBCTRAfterSet()
61 if (!MCID->isBranch()) in isBCTRAfterSet()
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst() argument
92 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1) in mustComeFirst()
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother() local
[all …]
DPPCHazardRecognizers.h33 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp214 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef() argument
215 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
549 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
550 if (MCID.hasOptionalDef() && in ReduceSpecial()
551 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
698 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
699 if (MCID.hasOptionalDef()) { in ReduceTo2Addr()
700 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
726 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
[all …]
DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
26 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
DMLxExpansionPass.cpp187 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
191 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
344 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
DThumb2ITBlockPass.cpp142 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
/external/llvm/lib/Target/NVPTX/
DNVPTXReplaceImageHandles.cpp81 const MCInstrDesc &MCID = MI.getDesc(); in processInstr() local
83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
130 if (!MCID) { in getHazardType()
134 unsigned idx = MCID->getSchedClass(); in getHazardType()
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
186 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction()
187 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction()
194 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
DTargetInstrInfo.cpp43 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() argument
46 if (OpNum >= MCID.getNumOperands()) in getRegClass()
49 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass()
50 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass()
124 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
125 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
187 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
188 if (!MCID.isCommutable()) in findCommutedOpIndices()
192 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
222 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
[all …]
DMachineInstr.cpp577 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
578 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()
580 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
581 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) in addImplicitDefUseOperands()
590 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0), in MachineInstr()
596 if (unsigned NumOps = MCID->getNumOperands() + in MachineInstr()
597 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { in MachineInstr()
609 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0), in MachineInstr()
677 assert(MCID && "Cannot add operands before providing an instr descriptor"); in addOperand()
709 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || in addOperand()
[all …]
DMachineVerifier.cpp770 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
771 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
773 errs() << MCID.getNumOperands() << " operands expected, but " in visitMachineInstrBefore()
814 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local
817 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
818 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
825 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
826 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
830 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { in visitMachineOperand()
837 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
[all …]
/external/tcpdump/tests/
Devb.out5 v3len 64, MCID Name Default, rev 0,
12 v3len 64, MCID Name Default, rev 0,
19 v3len 64, MCID Name Default, rev 0,
67 v3len 64, MCID Name Default, rev 0,
74 v3len 64, MCID Name Default, rev 0,
81 v3len 64, MCID Name Default, rev 0,
88 v3len 64, MCID Name Default, rev 0,
95 v3len 64, MCID Name Default, rev 0,
102 v3len 64, MCID Name Default, rev 0,
109 v3len 64, MCID Name Default, rev 0,
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrBuilder.h31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local
33 if (MCID.mayLoad()) in addFrameReference()
35 if (MCID.mayStore()) in addFrameReference()
DSystemZInstrInfo.cpp195 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleMove() local
196 if ((MCID.TSFlags & Flag) && in isSimpleMove()
624 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleBD12Move() local
625 return ((MCID.TSFlags & Flag) && in isSimpleBD12Move()
1125 const MCInstrDesc &MCID = get(Opcode); in getOpcodeForOffset() local
1126 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); in getOpcodeForOffset()
1144 if (MCID.TSFlags & SystemZII::Has20BitOffset) in getOpcodeForOffset()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
259 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
260 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
265 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
441 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
442 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
443 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
444 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
520 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
521 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
[all …]
DScheduleDAGRRList.cpp1003 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
1004 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
1005 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
1010 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
1198 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1199 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1200 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1201 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1326 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
1327 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
[all …]
DInstrEmitter.cpp324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() local
325 bool isOptDef = IIOpNum < MCID.getNumOperands() && in AddRegisterOperand()
326 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
361 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
854 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
855 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
856 MCID.getImplicitUses() + MCID.getNumImplicitUses()); in EmitMachineNode()
DScheduleDAGSDNodes.cpp299 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
300 if (MCID.mayLoad()) in ClusterNodes()
434 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in AddSchedEdges()
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
441 if (MCID.isCommutable()) in AddSchedEdges()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h153 const MCInstrDesc &MCID = MI->getDesc(); variable
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
/external/llvm/lib/Target/AArch64/
DAArch64ConditionalCompares.cpp593 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); in convert()
598 BuildMI(*Head, Head->end(), TermDL, MCID) in convert()
605 TII->getRegClass(MCID, 1, TRI, *MF)); in convert()
650 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
652 TII->getRegClass(MCID, 0, TRI, *MF)); in convert()
655 TII->getRegClass(MCID, 1, TRI, *MF)); in convert()
657 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID) in convert()
DAArch64RegisterInfo.cpp341 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); in materializeFrameBaseRegister() local
343 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
346 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp102 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr()

123