| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); in isRegFormat()
716 case X86Local::MRM0r: in emitInstructionSpecifier()
853 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
857 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 296 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
686 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 896 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1394 case X86II::MRM0r: case X86II::MRM1r: in EncodeInstruction()
1405 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, in EncodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 471 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
474 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
477 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
480 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
485 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
488 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
492 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
496 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
503 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
507 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
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| D | X86InstrFPStack.td | 238 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;
239 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;
240 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;
353 def CMOVB_F : FPI<0xDA, MRM0r, (outs RST:$op), (ins),
361 def CMOVNB_F : FPI<0xDB, MRM0r, (outs RST:$op), (ins),
509 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>;
602 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
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| D | X86InstrSystem.td | 406 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
410 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
415 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
541 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
544 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
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| D | X86InstrArithmetic.td | 455 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
460 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
464 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
468 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
1190 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1230 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1231 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1232 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1233 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
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| D | X86InstrInfo.td | 995 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
999 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1054 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1247 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1259 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1261 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1263 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
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| D | X86InstrFormats.td | 30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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| D | X86InstrAVX512.td | 3530 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>;
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1820 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
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