| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 120 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
127 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
134 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
245 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
295 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
307 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
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| D | X86InstrShiftRotate.td | 20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
57 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
59 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
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| D | X86InstrSystem.td | 380 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
450 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
452 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
455 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
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| D | X86InstrFPStack.td | 244 def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;
245 def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
246 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;
559 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
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| D | X86InstrMMX.td | 497 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
500 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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| D | X86InstrArithmetic.td | 61 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
69 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
74 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
80 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
1184 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
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| D | X86InstrInfo.td | 1504 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1508 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1512 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
2349 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
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| D | X86InstrFormats.td | 31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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| D | X86InstrSSE.td | 4112 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4115 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4158 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4161 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4204 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4207 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
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| D | X86InstrAVX512.td | 3527 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x73, MRM4r, MRM4m, "vpsra", X86vsrai>,
3528 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>;
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
109 "shl $dst, CL", 0xD2, MRM4r,
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 297 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
688 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 898 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1396 case X86II::MRM4r: case X86II::MRM5r: in EncodeInstruction()
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
720 case X86Local::MRM4r: in emitInstructionSpecifier()
855 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1822 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
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