| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 297 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
688 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 898 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1396 case X86II::MRM4r: case X86II::MRM5r: in EncodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
140 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
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| D | X86InstrFPStack.td | 241 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">;
242 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
243 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">;
561 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
568 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
570 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
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| D | X86InstrArithmetic.td | 113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
117 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
121 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
125 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
1193 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
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| D | X86InstrSystem.td | 384 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
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| D | X86InstrInfo.td | 1648 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1651 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1654 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
2343 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
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| D | X86InstrFormats.td | 31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
721 case X86Local::MRM5r: in emitInstructionSpecifier()
855 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1822 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
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