| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 99 const MemOpQueue &MemOps, unsigned DefReg,
112 MemOpQueue &MemOps,
128 unsigned Scratch, MemOpQueue &MemOps,
130 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
681 SmallVectorImpl<MachineOperand *> &UsesOfImpDefs, const MemOpQueue &MemOps, in findUsesOfImpDef() argument
690 for (unsigned i = 0; i < MemOps.size(); ++i) { in findUsesOfImpDef()
691 MachineInstr &MI = *MemOps[i].MBBI; in findUsesOfImpDef()
692 unsigned MIPosition = MemOps[i].Position; in findUsesOfImpDef()
834 unsigned Scratch, MemOpQueue &MemOps, in MergeLDR_STR() argument
837 int Offset = MemOps[SIndex].Offset; in MergeLDR_STR()
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| D | ARMISelLowering.cpp | 2875 SmallVector<SDValue, 4> MemOps; in StoreByValRegs() local
2885 MemOps.push_back(Store); in StoreByValRegs()
2890 if (!MemOps.empty()) in StoreByValRegs()
2891 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in StoreByValRegs()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | memops2.ll | 2 ; Generate MemOps for V4 and above.
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| D | memops3.ll | 2 ; Generate MemOps for V4 and above.
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| D | memops1.ll | 2 ; Generate MemOps for V4 and above.
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| D | memops.ll | 2 ; Generate MemOps for V4 and above.
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 3901 static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps, in FindOptimalMemOpLowering() argument
3997 MemOps.push_back(VT); in FindOptimalMemOpLowering()
4020 std::vector<EVT> MemOps; in getMemcpyLoadsAndStores() local
4036 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, in getMemcpyLoadsAndStores()
4043 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); in getMemcpyLoadsAndStores()
4063 unsigned NumMemOps = MemOps.size(); in getMemcpyLoadsAndStores()
4066 EVT VT = MemOps[i]; in getMemcpyLoadsAndStores()
4133 std::vector<EVT> MemOps; in getMemmoveLoadsAndStores() local
4146 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, in getMemmoveLoadsAndStores()
4152 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); in getMemmoveLoadsAndStores()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1316 SmallVector<SDValue, 4> MemOps; in LowerCCCArguments() local
1396 MemOps.push_back(Store); in LowerCCCArguments()
1424 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, in LowerCCCArguments()
1435 if (!MemOps.empty()) { in LowerCCCArguments()
1436 MemOps.push_back(Chain); in LowerCCCArguments()
1437 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerCCCArguments()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 786 SDValue MemOps[SystemZ::NumArgFPRs]; in LowerFormalArguments() local
794 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN, in LowerFormalArguments()
801 makeArrayRef(&MemOps[NumFixedFPRs], in LowerFormalArguments()
2199 SDValue MemOps[NumFields]; in lowerVASTART() local
2206 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr, in lowerVASTART()
2211 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in lowerVASTART()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2747 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_32SVR4() local
2792 MemOps.push_back(Store); in LowerFormalArguments_32SVR4()
2811 MemOps.push_back(Store); in LowerFormalArguments_32SVR4()
2819 if (!MemOps.empty()) in LowerFormalArguments_32SVR4()
2820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_32SVR4()
2910 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_64SVR4() local
3014 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
3041 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
3231 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
3238 if (!MemOps.empty()) in LowerFormalArguments_64SVR4()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2256 SmallVector<SDValue, 8> MemOps; in saveVarArgRegisters() local
2277 MemOps.push_back(Store); in saveVarArgRegisters()
2306 MemOps.push_back(Store); in saveVarArgRegisters()
2315 if (!MemOps.empty()) { in saveVarArgRegisters()
2316 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in saveVarArgRegisters()
3918 SmallVector<SDValue, 4> MemOps; in LowerAAPCS_VASTART() local
3923 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, in LowerAAPCS_VASTART()
3938 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, in LowerAAPCS_VASTART()
3953 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, in LowerAAPCS_VASTART()
3960 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32), in LowerAAPCS_VASTART()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 868 SmallVector<SDValue, 4> MemOps; in LowerFormalArguments() local
932 if (!MemOps.empty()) in LowerFormalArguments()
933 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments()
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| D | HexagonInstrInfoV4.td | 3124 // Define 'def Pats' for MemOps with register addend.
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 2489 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments() local
2501 MemOps.push_back(Store); in LowerFormalArguments()
2516 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, in LowerFormalArguments()
2520 if (!MemOps.empty()) in LowerFormalArguments()
2521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments()
14399 SmallVector<SDValue, 8> MemOps; in LowerVASTART() local
14406 MemOps.push_back(Store); in LowerVASTART()
14415 MemOps.push_back(Store); in LowerVASTART()
14425 MemOps.push_back(Store); in LowerVASTART()
14434 MemOps.push_back(Store); in LowerVASTART()
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