Searched refs:Narrow (Results 1 – 14 of 14) sorted by relevance
577 ((Narrow, 8))593 ((Narrow, 8))609 ((Narrow, 8))625 ((Narrow, 8))
207 vmovn.s32 d30, q11 @Narrow row 1208 vmovn.s32 d31, q12 @Narrow row 2209 vmovn.s32 d0 , q13 @Narrow row 3210 vmovn.s32 d1 , q14 @Narrow row 4222 vmovn.u16 d14, q5 @I Narrow the comparison for row 1 and 2 blk 1223 vmovn.u16 d15, q6 @I Narrow the comparison for row 1 and 2 blk 2402 vmovn.s32 d30, q11 @Narrow row 1403 vmovn.s32 d31, q12 @Narrow row 2404 vmovn.s32 d0 , q13 @Narrow row 3405 vmovn.s32 d1 , q14 @Narrow row 4[all …]
24 void Narrow(Graph* graph, Node* node, MaybeHandle<Context> context);
207 void Typer::Narrow(Graph* graph, Node* start, MaybeHandle<Context> context) { in Narrow() function in v8::internal::compiler::Typer
1185 bool Narrow = VT.getSizeInBits() == 64; in SelectLoadLane() local1190 if (Narrow) in SelectLoadLane()1211 if (Narrow) in SelectLoadLane()1225 bool Narrow = VT.getSizeInBits() == 64; in SelectPostLoadLane() local1230 if (Narrow) in SelectPostLoadLane()1256 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()1264 if (Narrow) in SelectPostLoadLane()1280 bool Narrow = VT.getSizeInBits() == 64; in SelectStoreLane() local1285 if (Narrow) in SelectStoreLane()1310 bool Narrow = VT.getSizeInBits() == 64; in SelectPostStoreLane() local[all …]
352 // Vector Saturating Narrow358 // Vector Saturating Extract and Unsigned Narrow
3 ; Narrow tORR cannot be predicated and set CPSR at the same time!
1427 # Narrow1784 # Scalar Signed Saturating Extract Unsigned Narrow1794 # Scalar Signed Saturating Extract Signed Narrow1804 # Scalar Unsigned Saturating Extract Narrow1916 # Signed Saturating Shift Right Narrow (Immediate)1926 # Unsigned Saturating Shift Right Narrow (Immediate)1936 # Signed Saturating Rounded Shift Right Narrow (Immediate)1946 # Unsigned Saturating Rounded Shift Right Narrow (Immediate)1956 # Signed Saturating Shift Right Unsigned Narrow (Immediate)1966 # Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)[all …]
1348 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)1350 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)1352 // Signed Saturating Shift Right Unsigned Narrow (Immediate)1354 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)1532 // Scalar Signed Saturating Extract Unsigned Narrow1536 // Scalar Signed Saturating Extract Narrow1540 // Scalar Unsigned Saturating Extract Narrow
2496 // Narrow 2-register operations.2505 // Narrow 2-register intrinsics.3149 // Narrow shift by immediate.4073 // Neon Shift Narrow operations,4137 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)4139 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)4622 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)4624 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)5238 // VSHRN : Vector Shift Right and Narrow5263 // VRSHRN : Vector Rounding Shift Right and Narrow[all …]
1591 // 4.2.31 Advanced SIMD, Add and Shift with Narrow
22086 SDValue Narrow = N->getOperand(0); in WidenMaskArithmetic() local22087 EVT NarrowVT = Narrow->getValueType(0); in WidenMaskArithmetic()22091 if (Narrow->getOpcode() != ISD::XOR && in WidenMaskArithmetic()22092 Narrow->getOpcode() != ISD::AND && in WidenMaskArithmetic()22093 Narrow->getOpcode() != ISD::OR) in WidenMaskArithmetic()22096 SDValue N0 = Narrow->getOperand(0); in WidenMaskArithmetic()22097 SDValue N1 = Narrow->getOperand(1); in WidenMaskArithmetic()22098 SDLoc DL(Narrow); in WidenMaskArithmetic()22119 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT)) in WidenMaskArithmetic()22134 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1); in WidenMaskArithmetic()
5236 U+202F Narrow no-break space
475 value;dt;Nar;Narrow;nar488 value;ea;Na;Narrow