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Searched refs:NewSU (Results 1 – 2 of 2) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp221 SUnit *NewSU; in CopyAndMoveSuccessors() local
254 SUnit *NewSU = newSUnit(N); in CopyAndMoveSuccessors() local
256 N->setNodeId(NewSU->NodeNum); in CopyAndMoveSuccessors()
261 NewSU->isTwoAddress = true; in CopyAndMoveSuccessors()
266 NewSU->isCommutable = true; in CopyAndMoveSuccessors()
319 AddPred(NewSU, Pred); in CopyAndMoveSuccessors()
326 D.setSUnit(NewSU); in CopyAndMoveSuccessors()
342 AddPred(NewSU, D); in CopyAndMoveSuccessors()
347 if (NewSU->NumSuccsLeft == 0) { in CopyAndMoveSuccessors()
348 NewSU->isAvailable = true; in CopyAndMoveSuccessors()
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DScheduleDAGRRList.cpp945 SUnit *NewSU; in CopyAndMoveSuccessors() local
999 SUnit *NewSU = CreateNewSUnit(N); in CopyAndMoveSuccessors() local
1001 N->setNodeId(NewSU->NodeNum); in CopyAndMoveSuccessors()
1006 NewSU->isTwoAddress = true; in CopyAndMoveSuccessors()
1011 NewSU->isCommutable = true; in CopyAndMoveSuccessors()
1013 InitNumRegDefsLeft(NewSU); in CopyAndMoveSuccessors()
1014 computeLatency(NewSU); in CopyAndMoveSuccessors()
1055 AddPred(NewSU, Pred); in CopyAndMoveSuccessors()
1062 D.setSUnit(NewSU); in CopyAndMoveSuccessors()
1066 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0) in CopyAndMoveSuccessors()
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