| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 260 unsigned &Op3) { in Decode3OpInstruction() argument
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
539 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
552 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
565 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAGInfo.h | 59 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy() argument
76 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
92 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemset() argument
106 SDValue Op3, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandPredSpillCode.cpp | 103 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. in runOnMachineFunction() local
107 Hexagon::C6)->addOperand(Op3); in runOnMachineFunction()
225 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. in runOnMachineFunction() local
228 Hexagon::C6)->addOperand(Op3); in runOnMachineFunction()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreSelectionDAGInfo.h | 32 SDValue Op3, unsigned Align, bool isVolatile,
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 55 SDValue Op3, unsigned Align,
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 69 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
76 switch (Op3.getImm()) { in printInst()
109 if (Op2.isImm() && Op3.isImm()) { in printInst()
113 int64_t imms = Op3.getImm(); in printInst()
143 if (Op2.getImm() > Op3.getImm()) { in printInst()
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 882 SDValue Op3);
884 SDValue Op3, SDValue Op4);
886 SDValue Op3, SDValue Op4, SDValue Op5);
898 SDValue Op1, SDValue Op2, SDValue Op3);
913 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
915 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
936 SDValue Op1, SDValue Op2, SDValue Op3);
945 SDValue Op1, SDValue Op2, SDValue Op3);
952 SDValue Op3);
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| D | SelectionDAGNodes.h | 780 const SDValue &Op2, const SDValue &Op3) {
788 Ops[3].setInitial(Op3);
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3620 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3621 if (Op2.isReg() && Op3.isImm()) { in MatchAndEmitInstruction()
3622 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3642 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
3643 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
3644 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3652 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3655 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3656 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3671 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /external/llvm/lib/Target/R600/ |
| D | R600InstrFormats.td | 20 bit Op3 = 0;
45 let TSFlags{5} = Op3;
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| D | R600Instructions.td | 196 let Op3 = 1;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5426 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
5427 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
5433 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
5434 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
5440 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5441 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
5512 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
5514 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
5569 SDValue Op3) { in SelectNodeTo() argument
5571 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
[all …]
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| D | SelectionDAGBuilder.cpp | 4592 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
4598 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
4614 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
4620 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
4636 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
4642 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
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| D | LegalizeIntegerTypes.cpp | 222 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); in PromoteIntRes_AtomicCmpSwap() local
227 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(), in PromoteIntRes_AtomicCmpSwap()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 22 bit Op3 = 0;
35 let TSFlags{5} = Op3;
107 let Op3 = 1;
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| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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| /external/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 1714 if (const ConstantFP *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall() local
1721 Op3->getValueAPF(), in ConstantFoldScalarCall()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2824 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
2830 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
2838 OutOps.push_back(Op3); in SelectInlineAsmMemoryOperand()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5913 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction() local
5919 if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) { in ParseInstruction()
5940 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction() local
5941 if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) { in ParseInstruction()
5949 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction() local
5950 if (Op3.isMem()) { in ParseInstruction()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 162 uint64_t imm2, unsigned Op3, bool Op3IsKill) { in fastEmitInst_riir() argument
|