Searched refs:Op5 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandPredSpillCode.cpp | 147 MachineOperand &Op5 = MI->getOperand(5); in runOnMachineFunction() local
157 NewMI->addOperand(Op5); in runOnMachineFunction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 886 SDValue Op3, SDValue Op4, SDValue Op5);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5440 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5441 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5915 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]); in ParseInstruction() local
5923 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) { in ParseInstruction()
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