Home
last modified time | relevance | path

Searched refs:OpVT (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp435 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
436 if (OpVT == MVT::f16) { in getFPEXT()
439 } else if (OpVT == MVT::f32) { in getFPEXT()
444 } else if (OpVT == MVT::f64) { in getFPEXT()
454 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { in getFPROUND() argument
456 if (OpVT == MVT::f32) in getFPROUND()
458 if (OpVT == MVT::f64) in getFPROUND()
460 if (OpVT == MVT::f80) in getFPROUND()
462 if (OpVT == MVT::f128) in getFPROUND()
464 if (OpVT == MVT::ppcf128) in getFPROUND()
[all …]
/external/llvm/include/llvm/CodeGen/
DRuntimeLibcalls.h407 Libcall getFPEXT(EVT OpVT, EVT RetVT);
411 Libcall getFPROUND(EVT OpVT, EVT RetVT);
415 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
419 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
423 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
427 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
DSelectionDAG.h608 SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT);
/external/llvm/lib/Target/X86/
DX86InstrFMA.td131 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
140 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
148 (OpVT (OpNode RC:$src2, RC:$src1,
155 SDNode OpNode, RegisterClass RC, ValueType OpVT,
160 x86memop, RC, OpVT, mem_frag>;
164 x86memop, RC, OpVT, mem_frag,
172 x86memop, RC, OpVT, mem_frag,
220 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
228 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
DX86InstrAVX512.td778 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
783 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
789 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
795 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
800 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
961 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
968 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
975 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
993 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
1000 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
[all …]
DX86ISelLowering.cpp10721 MVT OpVT = Op.getSimpleValueType(); in LowerSCALAR_TO_VECTOR() local
10725 if (!OpVT.is128BitVector()) { in LowerSCALAR_TO_VECTOR()
10727 unsigned SizeFactor = OpVT.getSizeInBits()/128; in LowerSCALAR_TO_VECTOR()
10728 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(), in LowerSCALAR_TO_VECTOR()
10729 OpVT.getVectorNumElements() / SizeFactor); in LowerSCALAR_TO_VECTOR()
10734 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); in LowerSCALAR_TO_VECTOR()
10737 if (OpVT == MVT::v1i64 && in LowerSCALAR_TO_VECTOR()
10742 assert(OpVT.is128BitVector() && "Expected an SSE type!"); in LowerSCALAR_TO_VECTOR()
10743 return DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerSCALAR_TO_VECTOR()
10790 MVT OpVT = Op.getSimpleValueType(); in LowerINSERT_SUBVECTOR() local
[all …]
DX86InstrSSE.td2812 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2821 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2828 [(set RC:$dst, (OpVT (OpNode RC:$src1,
5563 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5572 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5580 (OpVT (OpNode RC:$src1,
6792 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6801 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6809 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6977 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelDAGToDAG.cpp165 EVT OpVT = N->getValueType(0); in Select() local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI); in Select()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp464 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
465 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
466 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
DLegalizeFloatTypes.cpp1588 static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT) { in GetPromotionOpcode() argument
1589 if (OpVT == MVT::f16) { in GetPromotionOpcode()
1627 EVT OpVT = Op->getValueType(0); in PromoteFloatOp_BITCAST() local
1629 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); in PromoteFloatOp_BITCAST()
1636 return DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N), IVT, in PromoteFloatOp_BITCAST()
1935 EVT OpVT = Op->getValueType(0); in PromoteFloatRes_FP_ROUND() local
1940 SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op); in PromoteFloatRes_FP_ROUND()
DLegalizeVectorTypes.cpp241 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_UnaryOp() local
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_UnaryOp()
253 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_UnaryOp()
294 EVT OpVT = Cond->getOperand(0)->getValueType(0); in ScalarizeVecRes_VSELECT() local
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType()); in ScalarizeVecRes_VSELECT()
296 VecBool = TLI.getBooleanContents(OpVT); in ScalarizeVecRes_VSELECT()
377 EVT OpVT = LHS.getValueType(); in ScalarizeVecRes_VSETCC() local
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_VSETCC()
386 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_VSETCC()
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT)); in ScalarizeVecRes_VSETCC()
DLegalizeDAG.cpp1215 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType(); in LegalizeOp() local
1218 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
1224 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
1679 MVT OpVT = LHS.getSimpleValueType(); in LegalizeSetCCCondCode() local
1682 switch (TLI.getCondCodeAction(CCCode, OpVT)) { in LegalizeSetCCCondCode()
1689 if (TLI.isCondCodeLegal(InvCC, OpVT)) { in LegalizeSetCCCondCode()
1699 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT) in LegalizeSetCCCondCode()
1704 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT) in LegalizeSetCCCondCode()
1721 if (!OpVT.isInteger()) { in LegalizeSetCCCondCode()
1741 if (TLI.isCondCodeLegal(InvCC, OpVT)) { in LegalizeSetCCCondCode()
[all …]
DLegalizeTypes.cpp280 EVT OpVT = N->getOperand(i).getValueType(); in run() local
281 switch (getTypeAction(OpVT)) { in run()
DDAGCombiner.cpp7942 EVT OpVT = N0.getValueType(); in visitSINT_TO_FP() local
7953 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
7954 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
7994 EVT OpVT = N0.getValueType(); in visitUINT_TO_FP() local
8005 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
8006 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
10889 EVT OpVT = Ops[0].getValueType(); in visitINSERT_VECTOR_ELT() local
10890 if (InVal.getValueType() != OpVT) in visitINSERT_VECTOR_ELT()
10891 InVal = OpVT.bitsGT(InVal.getValueType()) ? in visitINSERT_VECTOR_ELT()
10892 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in visitINSERT_VECTOR_ELT()
[all …]
DSelectionDAGBuilder.cpp6308 MVT OpVT = MVT::Other; in visitInlineAsm() local
6323 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo)); in visitInlineAsm()
6326 OpVT = TLI.getSimpleValueType(CS.getType()); in visitInlineAsm()
6347 OpVT = in visitInlineAsm()
6351 OpInfo.ConstraintVT = OpVT; in visitInlineAsm()
DTargetLowering.cpp1151 EVT OpVT = Val.getValueType(); in ValueHasExactlyOneBitSet() local
1152 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); in ValueHasExactlyOneBitSet()
DLegalizeIntegerTypes.cpp1067 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy; in PromoteIntOp_SELECT() local
1068 Cond = PromoteTargetBoolean(Cond, OpVT); in PromoteIntOp_SELECT()
DSelectionDAG.cpp1016 EVT OpVT) { in getBoolExtOrTrunc() argument
1020 TargetLowering::BooleanContent BType = TLI->getBooleanContents(OpVT); in getBoolExtOrTrunc()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2222 EVT OpVT = Op.getOperand(0).getValueType(); in LowerSINT_TO_FP() local
2223 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2225 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2229 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { in LowerSINT_TO_FP()
2230 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2237 if (!TLI.isTypeLegal(OpVT)) in LowerSINT_TO_FP()
2242 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2271 EVT OpVT = Op.getOperand(0).getValueType(); in LowerUINT_TO_FP() local
2272 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2276 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp723 EVT OpVT = Op0.getValueType(); in SelectZeroExtend() local
724 unsigned OpBW = OpVT.getSizeInBits(); in SelectZeroExtend()
727 if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) { in SelectZeroExtend()
729 unsigned NE = OpVT.getVectorNumElements(); in SelectZeroExtend()
DHexagonISelLowering.cpp1046 EVT OpVT = Op1.getValueType(); in LowerVSELECT() local
1049 if (OpVT == MVT::v2i16) { in LowerVSELECT()
/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp1921 EVT OpVT = Ops[0].getValueType(); in PerformDAGCombine() local
1922 if (InVal.getValueType() != OpVT) in PerformDAGCombine()
1923 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
1924 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in PerformDAGCombine()
1925 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); in PerformDAGCombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp3884 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN() local
3886 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3887 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
3894 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3895 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
3901 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
3902 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
3907 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, in LowerFCOPYSIGN()
3908 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
3910 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, in LowerFCOPYSIGN()
[all …]
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp1752 MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i]; in ApplyTypeConstraints() local
1754 MadeChange |= getChild(i+1)->UpdateNodeType(0, OpVT, TP); in ApplyTypeConstraints()