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Searched refs:OperandCycles (Results 1 – 15 of 15) sorted by relevance

/external/llvm/include/llvm/MC/
DMCInstrItineraries.h113 const unsigned *OperandCycles; ///< Array of operand cycles selected variable
120 Stages(nullptr), OperandCycles(nullptr), in InstrItineraryData()
125 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F), in InstrItineraryData()
179 return (int)OperandCycles[FirstIdx + OperandIdx]; in getOperandCycle()
DMCSubtargetInfo.h43 const unsigned *OperandCycles; // Itinerary operand cycles variable
/external/llvm/lib/MC/
DMCSubtargetInfo.cpp58 OperandCycles = OC; in InitMCSubtargetInfo()
109 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); in getInstrItineraryForCPU()
115 InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths); in initInstrItins()
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td163 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
165 // This is overriden by OperandCycles if the
DPPCScheduleE500mc.td314 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
316 // This is overriden by OperandCycles if the
DPPCScheduleE5500.td374 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
376 // This is overriden by OperandCycles if the
DPPCScheduleG5.td123 // This is overriden by OperandCycles if the
DPPCSchedule440.td600 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
602 // This is overriden by OperandCycles if the
DPPCScheduleP8.td392 // This is overriden by OperandCycles if the
DPPCScheduleP7.td383 // This is overriden by OperandCycles if the
/external/llvm/include/llvm/Target/
DTargetItinerary.td93 // OperandCycles are optional "cycle counts". They specify the cycle after
116 list<int> OperandCycles = operandcycles;
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td22 let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
24 // This is overriden by OperandCycles if the
/external/llvm/lib/Target/X86/
DX86ScheduleAtom.td540 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
541 let HighLatency = 30;// Expected, may be overriden by OperandCycles.
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td1068 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
1070 // This is overriden by OperandCycles if the
DARMScheduleA9.td1892 // This is overriden by OperandCycles if the