Searched refs:OrigVT (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1353 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
1354 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 4041 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
4042 if (OrigVT.getSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
4047 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
4048 if (OrigVT.getSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 256 EVT OrigVT = VT; in ExpandConstantFP() local
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
264 TLI.ShouldShrinkFPConstant(OrigVT)) { in ExpandConstantFP()
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2467 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, in CalculateStackSlotAlignment() argument
2499 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
2500 Align = OrigVT.getStoreSize(); in CalculateStackSlotAlignment()
2512 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, in CalculateStackSlotUsed() argument
2524 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in CalculateStackSlotUsed()
2917 EVT OrigVT = Ins[ArgNo].ArgVT; in LowerFormalArguments_64SVR4() local
2931 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); in LowerFormalArguments_64SVR4()
4588 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
4633 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in LowerCall_64SVR4()
4696 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1726 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
1727 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
1728 return OrigVT; in getExtensionTo64Bits()
1730 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
1732 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5752 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
5753 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
5754 return OrigVT; in getExtensionTo64Bits()
5756 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
5758 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 8913 MVT OrigVT = V.getSimpleValueType(); in splitAndLowerVectorShuffle() local
8914 int OrigNumElements = OrigVT.getVectorNumElements(); in splitAndLowerVectorShuffle()
8916 MVT OrigScalarVT = OrigVT.getScalarType(); in splitAndLowerVectorShuffle()
23842 MVT OrigVT = OrigV.getSimpleValueType(); in performVZEXTCombine() local
23844 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) { in performVZEXTCombine()
23845 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits(); in performVZEXTCombine()
23846 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(), in performVZEXTCombine()
23847 OrigVT.getVectorNumElements() / Ratio); in performVZEXTCombine()
23848 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV, in performVZEXTCombine()
|