| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 52 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
397 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
398 OutMI.setOpcode(MI->getOpcode()); in Lower()
436 OutMI.addOperand(MCOp); in Lower()
441 switch (OutMI.getOpcode()) { in Lower()
447 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
449 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
454 OutMI.setOpcode(X86::MOV32ri); in Lower()
471 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && in Lower()
472 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { in Lower()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMCInstLower.cpp | 166 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { in lowerLongBranchLUi()
167 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
170 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
173 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), in lowerLongBranchLUi()
179 lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode, in lowerLongBranchADDiu() argument
181 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
186 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
190 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), in lowerLongBranchADDiu()
195 MCInst &OutMI) const { in lowerLongBranch()
200 lowerLongBranchLUi(MI, OutMI); in lowerLongBranch()
[all …]
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| D | MipsMCInstLower.h | 34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
42 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
43 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
46 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/BPF/ |
| D | BPFMCInstLower.cpp | 44 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
45 OutMI.setOpcode(MI->getOpcode()); in Lower()
75 OutMI.addOperand(MCOp); in Lower()
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| D | BPFMCInstLower.h | 35 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUMCInstLower.cpp | 30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
31 OutMI.setOpcode(MI->getOpcode()); in lower()
54 OutMI.addOperand(MCOp); in lower()
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| D | AMDGPUMCInstLower.h | 24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcMCInstLower.cpp | 96 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
100 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
107 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
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| D | Sparc.h | 34 MCInst &OutMI,
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZMCInstLower.cpp | 94 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
95 OutMI.setOpcode(MI->getOpcode()); in lower()
100 OutMI.addOperand(lowerOperand(MO)); in lower()
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| D | SystemZMCInstLower.h | 33 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreMCInstLower.cpp | 107 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
108 OutMI.setOpcode(MI->getOpcode()); in Lower()
115 OutMI.addOperand(MCOp); in Lower()
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| D | XCoreMCInstLower.h | 33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430MCInstLower.cpp | 113 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
114 OutMI.setOpcode(MI->getOpcode()); in Lower()
155 OutMI.addOperand(MCOp); in Lower()
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| D | MSP430MCInstLower.h | 34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 118 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerARMMachineInstrToMCInst() argument
120 OutMI.setOpcode(MI->getOpcode()); in LowerARMMachineInstrToMCInst()
160 OutMI.addOperand(MCOp); in LowerARMMachineInstrToMCInst()
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| D | ARM.h | 43 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUMCInstLower.cpp | 43 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
53 OutMI.setOpcode(MCOpcode); in lower()
90 OutMI.addOperand(MCOp); in lower()
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| D | AMDGPUMCInstLower.h | 29 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCMCInstLower.cpp | 173 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerPPCMachineInstrToMCInst() argument
175 OutMI.setOpcode(MI->getOpcode()); in LowerPPCMachineInstrToMCInst()
217 OutMI.addOperand(MCOp); in LowerPPCMachineInstrToMCInst()
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| D | PPC.h | 45 void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64MCInstLower.cpp | 204 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
205 OutMI.setOpcode(MI->getOpcode()); in Lower()
210 OutMI.addOperand(MCOp); in Lower()
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| D | AArch64MCInstLower.h | 39 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXAsmPrinter.cpp | 231 void NVPTXAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) { in lowerToMCInst() argument
232 OutMI.setOpcode(MI->getOpcode()); in lowerToMCInst()
236 OutMI.addOperand(GetSymbolRef( in lowerToMCInst()
247 OutMI.addOperand(MCOp); in lowerToMCInst()
253 OutMI.addOperand(MCOp); in lowerToMCInst()
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| D | NVPTXAsmPrinter.h | 197 void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
|