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Searched refs:PIPE_CONTROL_DEPTH_STALL (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_batchbuffer.c384 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
398 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
419 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE); in gen7_emit_vs_workaround_flush()
Dbrw_queryobj.c103 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | in write_depth_count()
115 PIPE_CONTROL_DEPTH_STALL | in write_depth_count()
Dgen6_vs_state.c220 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | in upload_vs_state()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.c384 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
398 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
419 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE); in gen7_emit_vs_workaround_flush()
/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_batchbuffer.c384 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
398 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
419 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE); in gen7_emit_vs_workaround_flush()
Dintel_reg.h71 #define PIPE_CONTROL_DEPTH_STALL (1 << 13) macro