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Searched refs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_reg.h80 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) macro
/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen6_vs_state.c222 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in upload_vs_state()