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Searched refs:PredReg (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp104 ARMCC::CondCodes Pred, unsigned PredReg);
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
121 unsigned PredReg,
127 ARMCC::CondCodes Pred, unsigned PredReg,
382 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses() argument
451 .addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
470 .addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
482 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps() argument
590 .addImm(Pred).addReg(PredReg); in MergeOps()
600 .addImm(Pred).addReg(PredReg); in MergeOps()
[all …]
DThumb2InstrInfo.cpp60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
223 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
228 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
252 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
261 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
267 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
[all …]
DThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
106 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
113 PredReg, MIFlags); in emitLoadConstPool()
116 PredReg, MIFlags); in emitLoadConstPool()
DMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
DARMBaseRegisterInfo.cpp396 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
407 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
755 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
759 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
DThumb2SizeReduction.cpp581 unsigned PredReg = 0; in ReduceSpecial() local
582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
685 unsigned PredReg = 0; in ReduceTo2Addr() local
686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
782 unsigned PredReg = 0; in ReduceToNarrow() local
783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
DThumbRegisterInfo.h43 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
DThumb2InstrInfo.h73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
DThumb2ITBlockPass.cpp171 unsigned PredReg = 0; in InsertITInstructions() local
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
DARMBaseInstrInfo.h440 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
461 ARMCC::CondCodes Pred, unsigned PredReg,
467 ARMCC::CondCodes Pred, unsigned PredReg,
DARMFrameLowering.cpp120 unsigned PredReg = 0) { in emitRegPlusImmediate() argument
123 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
126 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
134 unsigned PredReg = 0) { in emitSPUpdate() argument
136 MIFlags, Pred, PredReg); in emitSPUpdate()
1792 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1794 Pred, PredReg); in eliminateCallFramePseudoInstr()
1797 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
1800 Pred, PredReg); in eliminateCallFramePseudoInstr()
DARMBaseRegisterInfo.h164 unsigned PredReg = 0,
DARMConstantIslandPass.cpp1358 unsigned PredReg = 0; in createNewWater() local
1359 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1365 DEBUG(unsigned PredReg; in createNewWater()
1366 assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL)); in createNewWater()
1809 unsigned PredReg = 0; in optimizeThumb2Branches() local
1810 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1828 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
DARMExpandPseudoInsts.cpp656 unsigned PredReg = 0; in ExpandMOV32BitImm() local
657 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
684 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
685 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
733 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
734 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
DARMBaseInstrInfo.cpp1733 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() argument
1736 PredReg = 0; in getInstrPredicate()
1740 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1763 unsigned PredReg = 0; in commuteInstruction() local
1764 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
1766 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstruction()
1948 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
1953 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
1975 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
DARMISelDAGToDAG.cpp2488 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2489 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select()
2755 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2756 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2775 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2776 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2794 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2795 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
/external/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp495 unsigned PredReg = Cond[Cond.size()-1].getReg(); in getLoopTripCount() local
496 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()