Searched refs:PrefReg (Results 1 – 4 of 4) sorted by relevance
79 PrefReg, ///< Block entry/exit prefers a register. enumerator
135 case PrefReg: in addBias()
913 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()914 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()1133 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); in calcGlobalSplitCost()1135 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); in calcGlobalSplitCost()
623 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument626 RegAllocHints[VReg].second = PrefReg; in setRegAllocationHint()