| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 81 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
86 if (!RCI.Order) in compute()
87 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
112 RCI.Order[N++] = PhysReg; in compute()
116 RCI.NumRegs = N + CSRAlias.size(); in compute()
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
130 if (StressRA && RCI.NumRegs > StressRA) in compute()
131 RCI.NumRegs = StressRA; in compute()
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
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| D | TargetRegisterInfo.cpp | 193 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) in getMatchingSuperRegClass() local
194 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
197 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); in getMatchingSuperRegClass()
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| D | RegisterPressure.cpp | 188 RCI = rci; in init()
627 const RegisterClassInfo *RCI, in computeExcessPressureDelta() argument
637 unsigned Limit = RCI->getRegPressureSetLimit(i); in computeExcessPressureDelta()
769 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxUpwardPressureDelta()
835 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); in getUpwardPressureDelta()
963 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxDownwardPressureDelta()
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| D | PostRASchedulerList.cpp | 196 const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
212 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
214 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr)); in SchedulePostRATDList()
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| D | AggressiveAntiDepBreaker.h | 128 const RegisterClassInfo &RCI,
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| D | CriticalAntiDepBreaker.cpp | 31 const RegisterClassInfo &RCI) in CriticalAntiDepBreaker() argument
34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
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| D | RegAllocGreedy.cpp | 113 RegisterClassInfo RCI; member in __anon4e4d313f0111::RAGreedy
1521 const RegisterClassInfo &RCI) { in getNumAllocatableRegsForConstraints() argument
1529 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
1560 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1570 TRI, RCI)) { in tryInstructionSplit()
2529 RCI.runOnMachineFunction(mf); in runOnMachineFunction()
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| D | TargetLoweringBase.cpp | 1160 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) in findRepresentativeClass() local
1161 SuperRegRC.setBitsInMask(RCI.getMask()); in findRepresentativeClass()
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| D | AggressiveAntiDepBreaker.cpp | 114 MachineFunction &MFi, const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in AggressiveAntiDepBreaker()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 71 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
72 if (Tag != RCI.Tag) in get()
74 return RCI; in get()
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| D | RegisterPressure.h | 238 const RegisterClassInfo *RCI;
273 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
277 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
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| /external/llvm/lib/Transforms/Scalar/ |
| D | ConstantHoisting.cpp | 245 for (auto const &RCI : ConstInfo.RebasedConstants) in findConstantInsertionPoint() local
246 for (auto const &U : RCI.Uses) in findConstantInsertionPoint()
554 for (auto const &RCI : ConstInfo.RebasedConstants) { in emitBaseConstants() local
556 for (auto const &U : RCI.Uses) in emitBaseConstants()
557 emitBaseConstants(Base, RCI.Offset, U); in emitBaseConstants()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 118 RegisterClassInfo RCI; member in __anon32224d0b0111::AArch64A57FPLoadBalancing
320 RCI.runOnMachineFunction(F); in runOnMachineFunction()
521 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2208 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint() local
2209 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
2210 const TargetRegisterClass *RC = *RCI; in getRegForInlineAsmConstraint()
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