| /external/llvm/include/llvm/Target/ |
| D | TargetOpcodes.h | 82 REG_SEQUENCE = 12, enumerator
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| /external/llvm/test/CodeGen/R600/ |
| D | sgpr-copy-duplicate-operand.ll | 5 ; used in an REG_SEQUENCE that also needs to be handled.
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| D | literals.ll | 37 ; Make sure inline literals are folded into REG_SEQUENCE instructions.
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| D | si-lod-bias.ll | 5 ; the wrong register class is used for the REG_SEQUENCE instructions.
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| D | smrd.ll | 45 ; through REG_SEQUENCE
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-01-24-RegSequenceLiveRange.ll | 7 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
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| D | crash.ll | 31 ; PR10520 - REG_SEQUENCE with implicit-def operands.
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| D | reg_sequence.ll | 3 ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
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| D | coalesce-subregs.ll | 72 ; The trivial REG_SEQUENCE lowering can't handle that, but the coalescer can.
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 1378 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; in getVALUOp()
1456 case AMDGPU::REG_SEQUENCE: in canReadVGPR()
1560 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst) in split64BitImm()
1706 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE || in legalizeOperands()
1743 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) { in legalizeOperands()
1825 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands()
1891 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands()
1992 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE)) in splitSMRD()
2051 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc) in moveSMRDToVALU()
2281 case AMDGPU::REG_SEQUENCE: in moveToVALU()
[all …]
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| D | AMDGPUISelDAGToDAG.cpp | 179 case AMDGPU::REG_SEQUENCE: { in getOperandRegClass()
372 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), in Select()
393 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in Select()
421 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N), in Select()
787 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args); in SelectADD_SUB_I64()
1035 SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL, in SelectMUBUFScratch()
1148 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in SelectAddrSpaceCast()
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| D | R600OptimizeVectorRegisters.cpp | 68 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); in RegSeqInfo()
329 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) { in runOnMachineFunction()
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| D | SIFixSGPRCopies.cpp | 309 case AMDGPU::REG_SEQUENCE: { in runOnMachineFunction()
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| D | SIISelLowering.cpp | 1934 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) { in PostISelFolding()
2007 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, in wrapAddr64Rsrc()
2019 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); in wrapAddr64Rsrc()
2031 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); in wrapAddr64Rsrc()
2068 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); in buildRSRC()
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| D | SIInstructions.td | 2201 (i64 (REG_SEQUENCE SReg_64,
2646 (REG_SEQUENCE VReg_64,
2666 (REG_SEQUENCE VReg_64,
2676 (REG_SEQUENCE VReg_64,
2761 (REG_SEQUENCE VReg_128,
3226 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
3231 (REG_SEQUENCE VReg_64,
3244 (REG_SEQUENCE SReg_64, $src, sub0,
3250 (REG_SEQUENCE VReg_64,
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| D | AMDGPUInstructions.td | 563 (REG_SEQUENCE RC64,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 56 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
108 case TargetOpcode::REG_SEQUENCE: in reserveResources()
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| D | HexagonISelDAGToDAG.cpp | 1199 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in SelectBitOp()
1208 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in SelectBitOp()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 266 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
306 case TargetOpcode::REG_SEQUENCE: in reserveResources()
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| D | InstrEmitter.cpp | 610 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
738 if (Opc == TargetOpcode::REG_SEQUENCE) { in EmitMachineNode()
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| D | ScheduleDAGRRList.cpp | 298 if (Opcode == TargetOpcode::REG_SEQUENCE) { in GetCostForDef()
2121 Opc == TargetOpcode::REG_SEQUENCE || in unscheduledNode()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 773 return getOpcode() == TargetOpcode::REG_SEQUENCE;
812 case TargetOpcode::REG_SEQUENCE:
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1571 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1582 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
1592 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createDRegPairNode()
1602 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQRegPairNode()
1617 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadSRegsNode()
1631 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadDRegsNode()
1645 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadQRegsNode()
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| D | A15SDOptimizer.cpp | 474 TII->get(TargetOpcode::REG_SEQUENCE), Out) in createRegSequence()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 863 case TargetOpcode::REG_SEQUENCE: in getCopyRewriter()
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