Home
last modified time | relevance | path

Searched refs:RESULT (Results 1 – 25 of 77) sorted by relevance

1234

/external/llvm/test/CodeGen/R600/
Dcttz_zero_undef.ll15 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
16 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
25 ; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
26 ; SI: buffer_store_dword [[RESULT]],
28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
29 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
43 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
44 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
45 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
61 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
[all …]
Dctlz_zero_undef.ll15 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
16 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
25 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
26 ; SI: buffer_store_dword [[RESULT]],
28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
29 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
43 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
44 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
45 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
61 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
[all …]
Duse-sgpr-multiple-times.ll11 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
12 ; GCN: buffer_store_dword [[RESULT]]
21 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
22 ; GCN: buffer_store_dword [[RESULT]]
35 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
36 ; GCN: buffer_store_dword [[RESULT]]
49 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
50 ; GCN: buffer_store_dword [[RESULT]]
63 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
64 ; GCN: buffer_store_dword [[RESULT]]
[all …]
Dsetcc-opt.ll8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
9 ; GCN-NEXT:buffer_store_byte [[RESULT]]
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
26 ; GCN-NEXT: buffer_store_byte [[RESULT]]
74 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
75 ; GCN-NEXT: buffer_store_byte [[RESULT]]
88 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
89 ; GCN-NEXT: buffer_store_byte [[RESULT]]
102 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
103 ; GCN-NEXT: buffer_store_byte [[RESULT]]
[all …]
Dtrunc-cmp-constant.ll25 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
26 ; SI-NEXT: buffer_store_byte [[RESULT]]
36 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
37 ; SI: buffer_store_byte [[RESULT]]
48 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
49 ; SI-NEXT: buffer_store_byte [[RESULT]]
60 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
61 ; SI-NEXT: buffer_store_byte [[RESULT]]
71 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
72 ; SI: buffer_store_byte [[RESULT]]
[all …]
Dllvm.AMDGPU.fract.ll13 ; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
15 ; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
16 ; GCN: buffer_store_dword [[RESULT]]
26 ; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
28 ; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
29 ; GCN: buffer_store_dword [[RESULT]]
39 ; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]]
41 ; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]]
42 ; GCN: buffer_store_dword [[RESULT]]
53 ; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
[all …]
Dllvm.AMDGPU.clamp.ll11 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
12 ; SI: buffer_store_dword [[RESULT]]
24 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
25 ; SI: buffer_store_dword [[RESULT]]
36 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
37 ; SI: buffer_store_dword [[RESULT]]
48 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
49 ; SI: buffer_store_dword [[RESULT]]
61 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
62 ; SI: buffer_store_dword [[RESULT]]
Dctpop.ll28 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
29 ; GCN: buffer_store_dword [[RESULT]],
44 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
45 ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
46 ; GCN: buffer_store_dword [[RESULT]],
64 ; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
65 ; GCN-NEXT: buffer_store_dword [[RESULT]],
177 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
178 ; GCN: buffer_store_dword [[RESULT]],
192 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
[all …]
Dllvm.AMDGPU.class.ll14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
15 ; SI-NEXT: buffer_store_dword [[RESULT]]
29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
30 ; SI-NEXT: buffer_store_dword [[RESULT]]
45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
46 ; SI-NEXT: buffer_store_dword [[RESULT]]
61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
62 ; SI-NEXT: buffer_store_dword [[RESULT]]
76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
77 ; SI-NEXT: buffer_store_dword [[RESULT]]
[all …]
Dscalar_to_vector.ll7 ; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]]
8 ; SI: buffer_store_short [[RESULT]]
9 ; SI: buffer_store_short [[RESULT]]
10 ; SI: buffer_store_short [[RESULT]]
11 ; SI: buffer_store_short [[RESULT]]
23 ; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]]
24 ; SI: buffer_store_short [[RESULT]]
25 ; SI: buffer_store_short [[RESULT]]
26 ; SI: buffer_store_short [[RESULT]]
27 ; SI: buffer_store_short [[RESULT]]
Dfmuladd.ll37 ; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
38 ; CHECK: buffer_store_dword [[RESULT]]
56 ; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
57 ; CHECK: buffer_store_dword [[RESULT]]
75 ; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
76 ; CHECK: buffer_store_dword [[RESULT]]
97 ; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
98 ; CHECK: buffer_store_dword [[RESULT]]
119 ; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], -2.0, [[R1]], [[R2]]
120 ; CHECK: buffer_store_dword [[RESULT]]
[all …]
Dfceil.ll14 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
15 ; EG: CEIL {{\*? *}}[[RESULT]]
25 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
26 ; EG: CEIL {{\*? *}}[[RESULT]]
27 ; EG: CEIL {{\*? *}}[[RESULT]]
55 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
56 ; EG: CEIL {{\*? *}}[[RESULT]]
57 ; EG: CEIL {{\*? *}}[[RESULT]]
58 ; EG: CEIL {{\*? *}}[[RESULT]]
59 ; EG: CEIL {{\*? *}}[[RESULT]]
Dshl_add_constant.ll9 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], 36, [[REG]]
10 ; SI: buffer_store_dword [[RESULT]]
43 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], 0xf9c, [[REG]]
44 ; SI: buffer_store_dword [[RESULT]]
61 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
62 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
77 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
78 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
Dmad-combine.ll22 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
24 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
30 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
32 ; SI: buffer_store_dword [[RESULT]]
99 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
100 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
103 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
105 ; SI: buffer_store_dword [[RESULT]]
129 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
130 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
[all …]
Dfp16_to_fp.ll9 ; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
10 ; SI: buffer_store_dword [[RESULT]]
22 ; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
23 ; SI: buffer_store_dwordx2 [[RESULT]]
Dmad-sub.ll10 ; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
11 ; SI: buffer_store_dword [[RESULT]]
34 ; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
35 ; SI: buffer_store_dword [[RESULT]]
79 ; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
80 ; SI: buffer_store_dword [[RESULT]]
104 ; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
105 ; SI: buffer_store_dword [[RESULT]]
151 ; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
152 ; SI: buffer_store_dword [[RESULT]]
[all …]
Dllvm.AMDGPU.trig_preop.ll9 ; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
10 ; SI: buffer_store_dwordx2 [[RESULT]],
22 ; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
23 ; SI: buffer_store_dwordx2 [[RESULT]],
Dfmax3.ll10 ; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
11 ; SI: buffer_store_dword [[RESULT]],
28 ; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
29 ; SI: buffer_store_dword [[RESULT]],
Dfmin3.ll11 ; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
12 ; SI: buffer_store_dword [[RESULT]],
29 ; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
30 ; SI: buffer_store_dword [[RESULT]],
Dsint_to_fp.f64.ll31 ; SI-NEXT: v_cvt_f64_i32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
32 ; SI: buffer_store_dwordx2 [[RESULT]]
52 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
53 ; SI: buffer_store_dwordx2 [[RESULT]]
Dsint_to_fp.ll46 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
47 ; SI: buffer_store_dword [[RESULT]],
57 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0
58 ; SI: buffer_store_dword [[RESULT]],
Duint_to_fp.ll64 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
65 ; SI: buffer_store_dword [[RESULT]],
75 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0
76 ; SI: buffer_store_dword [[RESULT]],
Dds_read2st64.ll10 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
11 ; SI: buffer_store_dword [[RESULT]]
29 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
30 ; SI: buffer_store_dword [[RESULT]]
49 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
50 ; SI: buffer_store_dword [[RESULT]]
122 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_…
123 ; SI: buffer_store_dwordx2 [[RESULT]]
141 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_…
142 ; SI: buffer_store_dwordx2 [[RESULT]]
[all …]
Dllvm.AMDGPU.div_fmas.ll21 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
22 ; GCN: buffer_store_dword [[RESULT]],
35 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
36 ; SI: buffer_store_dword [[RESULT]],
49 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]]
50 ; SI: buffer_store_dword [[RESULT]],
63 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
64 ; SI: buffer_store_dword [[RESULT]],
/external/lldb/test/unittest2/test/
Dtest_program.py91 RESULT = object() variable
106 return RESULT
183 self.assertIs(program.result, RESULT)
197 self.assertIs(program.result, RESULT)
215 self.assertIs(program.result, RESULT)

1234