Searched refs:REV32 (Results 1 – 8 of 8) sorted by relevance
| /external/elfutils/src/backends/ |
| D | sparc_reloc.def | 121 RELOC_TYPE (REV32, REL)
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 106 REV32, enumerator
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| D | AArch64SchedCyclone.td | 147 // CLS,CLZ,RBIT,REV,REV16,REV32
497 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| D | AArch64ISelLowering.cpp | 830 case AArch64ISD::REV32: return "AArch64ISD::REV32"; in getTargetNodeName()
5047 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
5230 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 192 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
2649 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 194 ; vrev <4 x i16> should use REV32 and not REV64
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| /external/vixl/doc/ |
| D | supported-instructions.md | 968 ### REV32 ### subsection
2848 ### REV32 ### subsection
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| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 1823 REV32
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