Searched refs:REnd (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 147 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); in RemoveBranch() local
152 while (I != REnd && I->isDebugValue()) in RemoveBranch()
159 for (removed = 0; I != REnd && removed < 2; ++I, ++removed) in RemoveBranch()
183 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); in AnalyzeBranch() local
186 while (I != REnd && I->isDebugValue()) in AnalyzeBranch()
189 if (I == REnd || !isUnpredicatedTerminator(&*I)) { in AnalyzeBranch()
208 if (++I != REnd) { in AnalyzeBranch()
232 if (++I != REnd && isUnpredicatedTerminator(&*I)) in AnalyzeBranch()
|
| /external/llvm/include/llvm/ADT/ |
| D | ImmutableSet.h | 142 iterator RItr = RHS.begin(), REnd = RHS.end(); in isEqual() local
144 while (LItr != LEnd && RItr != REnd) { in isEqual()
158 return LItr == LEnd && RItr == REnd; in isEqual()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 315 for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; ++RIdx) { in collectSchedRW()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2860 unsigned RBegin, REnd; in StoreByValRegs() local
2862 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd); in StoreByValRegs()
2866 REnd = ARM::R4; in StoreByValRegs()
2869 if (REnd != RBegin) in StoreByValRegs()
2879 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) { in StoreByValRegs()
2964 unsigned RBegin, REnd; in LowerFormalArguments() local
2965 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd); in LowerFormalArguments()
|