Searched refs:ResultReg1 (Results 1 – 1 of 1) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3554 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0; in fastLowerIntrinsicCall() local
3559 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3563 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3567 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3571 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3638 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3640 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg); in fastLowerIntrinsicCall()
3647 assert((ResultReg1 + 1) == ResultReg2 && in fastLowerIntrinsicCall()
3649 updateValueMap(II, ResultReg1, 2); in fastLowerIntrinsicCall()
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