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Searched refs:SALU (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/R600/
DSIInstrFormats.td21 field bits<1> SALU = 0;
48 let TSFlags{3} = SALU;
230 let SALU = 1;
241 let SALU = 1;
254 let SALU = 1;
267 let SALU = 1;
279 let SALU = 1;
DSIDefines.h19 SALU = 1 << 3, enumerator
DSIInstrInfo.h143 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
/external/llvm/test/CodeGen/R600/
Dsplit-scalar-i64-add.ll6 ; SALU, but the upper half does not. The addc expects the carry bit
Dsgpr-control-flow.ll4 ; Most SALU instructions ignore control flow, so we need to make sure
Dctpop64.ll95 ; FIXME: We currently disallow SALU instructions in all branches,
Dxor.ll152 ; use an SALU instruction for this.
Dctpop.ll271 ; FIXME: We currently disallow SALU instructions in all branches,
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td26 // Special bitcast node for sharing VCC register between VALU and SALU