| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 SDIVREM, UDIVREM, enumerator
|
| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 895 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
897 Results.push_back(SDIVREM); in ReplaceNodeResults()
904 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
906 Results.push_back(SDIVREM.getValue(1)); in ReplaceNodeResults()
909 case ISD::SDIVREM: { in ReplaceNodeResults()
|
| D | AMDGPUISelLowering.cpp | 270 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
336 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
610 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1858 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 145 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
167 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 176 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
|
| D | LegalizeDAG.cpp | 2211 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in useDivRem()
2238 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3500 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3531 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3565 case ISD::SDIVREM: in ExpandNode()
|
| D | DAGCombiner.cpp | 1322 case ISD::SDIVREM: return visitSDIVREM(N); in visit()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
|
| D | MipsISelLowering.cpp | 405 setTargetDAGCombine(ISD::SDIVREM); in MipsTargetLowering()
460 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
795 case ISD::SDIVREM: in PerformDAGCombine()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 116 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1306 setOperationAction(ISD::SDIVREM, VT, Expand); in HexagonTargetLowering()
1638 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in HexagonTargetLowering()
1641 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in HexagonTargetLowering()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2436 case ISD::SDIVREM: in Select()
2443 bool isSigned = (Opcode == ISD::SDIVREM || in Select()
|
| D | X86ISelLowering.cpp | 706 setOperationAction(ISD::SDIVREM, VT, Expand); in X86TargetLowering()
1526 setOperationAction(ISD::SDIVREM, MVT::i128, Custom); in X86TargetLowering()
15969 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break; in LowerWin64_i128OP()
17305 case ISD::SDIVREM: in ReplaceNodeResults()
23250 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 && in PerformSExtCombine()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1409 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1416 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 155 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
2726 case ISD::SDIVREM: in LowerOperation()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 352 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 737 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
740 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
6328 case ISD::SDIVREM: in LowerOperation()
10753 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
10755 bool isSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
468 setOperationAction(ISD::SDIVREM, VT, Expand); in PPCTargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
|