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Searched refs:SLLV (Results 1 – 21 of 21) sorted by relevance

/external/valgrind/none/tests/mips64/
Dshift_instructions.c9 ROTR, ROTRV, SLL, SLLV, enumerator
170 case SLLV: in main()
/external/v8/src/mips/
Dconstants-mips.cc227 case SLLV: in InstructionType()
Dconstants-mips.h376 SLLV = ((0 << 3) + 4), enumerator
Ddisasm-mips.cc658 case SLLV: in DecodeTypeRegister()
Dsimulator-mips.cc1943 case SLLV: in ConfigureTypeRegister()
Dassembler-mips.cc1611 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
/external/v8/src/mips64/
Dconstants-mips64.cc233 case SLLV: in InstructionType()
Dconstants-mips64.h353 SLLV = ((0 << 3) + 4), enumerator
Ddisasm-mips64.cc723 case SLLV: in DecodeTypeRegister()
Dsimulator-mips64.cc2032 case SLLV: in ConfigureTypeRegister()
Dassembler-mips64.cc1675 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
/external/pcre/dist/sljit/
DsljitNativeMIPS_32.c328 EMIT_SHIFT(SLL, SLLV); in emit_single_op()
DsljitNativeMIPS_64.c423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
DsljitNativeMIPS_common.c166 #define SLLV (HI(0) | LO(4)) macro
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1224 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1227 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1466 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
1471 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
1475 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
DMipsInstrInfo.td1174 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1624 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
DMips16InstrInfo.td1155 // Format: SLLV ry, rx MIPS16e
/external/valgrind/none/tests/mips32/
DMIPS32int.stdout.exp-mips32-BE651 SLLV
DMIPS32int.stdout.exp-mips32-LE651 SLLV
DMIPS32int.stdout.exp-mips32r2-LE1129 SLLV
DMIPS32int.stdout.exp-mips32r2-BE1129 SLLV