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Searched refs:SREG (Results 1 – 9 of 9) sorted by relevance

/external/libunwind/src/mips/
Dgetcontext-android.S36 # define SREG(X) \ macro
46 # define SREG(X) sd $X, (LINUX_UC_MCONTEXT_GREGS + 8 * X) ($4) macro
56 SREG (0)
57 SREG (1)
58 SREG (2)
59 SREG (3)
60 SREG (4)
61 SREG (5)
62 SREG (6)
63 SREG (7)
[all …]
Dgetcontext.S37 # define SREG(X) \ macro
47 # define SREG(X) sd $X, (LINUX_UC_MCONTEXT_GREGS + 8 * X) ($4) macro
57 SREG (1)
58 SREG (0)
59 SREG (2)
60 SREG (3)
61 SREG (4)
62 SREG (5)
63 SREG (6)
64 SREG (7)
[all …]
/external/llvm/test/CodeGen/R600/
Dtrunc-store-i1.ll7 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
26 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
Dsetuo.ll5 ; CHECK: v_cmp_u_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]]
Dseto.ll5 ; CHECK: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]]
Dtrunc.ll23 ; SI-DAG: s_load_dword [[SREG:s[0-9]+]],
24 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
/external/llvm/test/CodeGen/AArch64/
Darm64-sitofp-combine-chains.ll14 ; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]],
Darm64-xaluo.ll196 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
197 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
366 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
367 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
556 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
557 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
/external/vixl/src/vixl/a64/
Dassembler-a64.cc182 #define SREG(n) s##n, macro
184 REGISTER_CODE_LIST(SREG)
186 #undef SREG