Searched refs:SRI (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
33 if (*SRI == Idx) in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
45 return *SRI; in getSubRegIndex()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 213 MCSuperRegIterator SRI(Reg, TRI); in uniqueSuperReg() local
214 assert(SRI.isValid() && "Expected a superreg"); in uniqueSuperReg()
215 unsigned SuperReg = *SRI; in uniqueSuperReg()
216 ++SRI; in uniqueSuperReg()
217 assert(!SRI.isValid() && "Expected exactly one superreg"); in uniqueSuperReg()
|
| /external/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 274 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
275 unsigned SubregReg = *SRI; in ScanInstruction()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 267 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
268 if (SRI == Map.end()) in computeSubRegs()
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
275 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
1439 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), in normalizeWeight() local
1440 SRE = SRM.end(); SRI != SRE; ++SRI) { in normalizeWeight()
1441 if (SRI->second == Reg) in normalizeWeight()
1444 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, in normalizeWeight()
|
| D | CodeGenSchedule.cpp | 287 for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) { in collectSchedRW() local
288 assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite"); in collectSchedRW()
289 SchedReads.push_back(CodeGenSchedRW(SchedReads.size(), *SRI)); in collectSchedRW()
|
| /external/iputils/doc/ |
| D | rdisc.sgml | 189 RFC1256</ulink>, Network Information Center, SRI International,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2682 unsigned SRI; in Select() local
2685 case 0: SRI = PPC::sub_lt; break; in Select()
2686 case 1: SRI = PPC::sub_gt; break; in Select()
2687 case 2: SRI = PPC::sub_eq; break; in Select()
2688 case 3: SRI = PPC::sub_un; break; in Select()
2691 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 494 // SLI,SRI
|
| D | AArch64InstrInfo.td | 4429 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4478 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 3610 ### SRI ### subsection
|