| /external/v8/src/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 220 __ Add(x10, input_end(), Operand(current_input_offset(), SXTW)); in CheckAtStart()
231 __ Add(x10, input_end(), Operand(current_input_offset(), SXTW)); in CheckNotAtStart()
257 Operand(current_input_offset(), SXTW)); in CheckCharacters()
321 Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
324 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
327 Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
362 __ Cmp(current_input_offset().X(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
384 __ Add(x0, input_end(), Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
388 __ Add(x1, input_end(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
440 __ Add(capture_start_address, input_end(), Operand(w10, SXTW)); in CheckNotBackReference()
[all …]
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| D | codegen-arm64.cc | 493 __ Ldrh(result, MemOperand(string, index, SXTW, 1)); in Generate()
497 __ Ldrb(result, MemOperand(string, index, SXTW)); in Generate()
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| D | lithium-codegen-arm64.cc | 1504 : Operand(ToRegister32(instr->right()), SXTW); in DoAddE()
1676 __ Ldr(scratch, MemOperand(elements, length, SXTW, kPointerSizeLog2)); in DoApplyArguments()
3027 __ Add(result, base, Operand(ToRegister32(instr->offset()), SXTW)); in DoInnerAllocatedObject()
3419 return MemOperand(base, key, SXTW, element_size_shift); in PrepareKeyedExternalArrayOperand()
3424 return MemOperand(scratch, key, SXTW, element_size_shift); in PrepareKeyedExternalArrayOperand()
3548 __ Add(base, elements, Operand(key, SXTW, element_size_shift)); in PrepareKeyedArrayOperand()
3552 return MemOperand(base, key, SXTW, element_size_shift); in PrepareKeyedArrayOperand()
3893 __ Cmp(result, Operand(result, SXTW)); in DoMathFloorI()
4168 __ Cmp(result, Operand(result.W(), SXTW)); in DoMathRoundI()
4463 __ Cmp(result.X(), Operand(result, SXTW)); in DoMulI()
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| D | assembler-arm64-inl.h | 475 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
528 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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| D | constants-arm64.h | 348 SXTW = 6, enumerator
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| D | disasm-arm64.cc | 1658 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | simulator-arm64.cc | 938 case SXTW: in ExtendValue()
1555 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | assembler-arm64.cc | 2405 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 47 SXTW, enumerator
66 case AArch64_AM::SXTW: return "sxtw"; in getShiftExtendName()
133 case 6: return AArch64_AM::SXTW; in getExtendType()
160 case AArch64_AM::SXTW: return 6; break; in getExtendEncoding()
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| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 145 COMPARE(Mov(x16, Operand(x20, SXTW, 3)), "sbfiz x16, x20, #3, #32"); in TEST_()
385 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); in TEST_()
411 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); in TEST_()
900 COMPARE(ldr(w12, MemOperand(x13, w14, SXTW)), "ldr w12, [x13, w14, sxtw]"); in TEST_()
901 COMPARE(ldr(w15, MemOperand(x16, w17, SXTW, 2)), in TEST_()
910 COMPARE(ldr(x12, MemOperand(x13, w14, SXTW)), "ldr x12, [x13, w14, sxtw]"); in TEST_()
911 COMPARE(ldr(x15, MemOperand(x16, w17, SXTW, 3)), in TEST_()
921 COMPARE(str(w12, MemOperand(x13, w14, SXTW)), "str w12, [x13, w14, sxtw]"); in TEST_()
922 COMPARE(str(w15, MemOperand(x16, w17, SXTW, 2)), in TEST_()
931 COMPARE(str(x12, MemOperand(x13, w14, SXTW)), "str x12, [x13, w14, sxtw]"); in TEST_()
[all …]
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| D | test-assembler-arm64.cc | 310 __ Mvn(x15, Operand(w2, SXTW, 4)); in TEST()
568 __ Orr(x12, x0, Operand(x1, SXTW, 2)); in TEST()
665 __ Orn(x12, x0, Operand(x1, SXTW, 2)); in TEST()
734 __ And(x12, x0, Operand(x1, SXTW, 2)); in TEST()
875 __ Bic(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1003 __ Eor(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1072 __ Eon(x12, x0, Operand(x1, SXTW, 2)); in TEST()
2690 __ Ldr(w3, MemOperand(x18, x27, SXTW)); in TEST()
2691 __ Ldr(w4, MemOperand(x18, x28, SXTW, 2)); in TEST()
2694 __ Str(w2, MemOperand(x20, x29, SXTW, 2)); in TEST()
[all …]
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| /external/vixl/test/ |
| D | test-disasm-a64.cc | 151 COMPARE(Mov(x16, Operand(x17, SXTW, 3)), "sbfiz x16, x17, #3, #32"); in TEST()
385 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); in TEST()
411 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); in TEST()
1016 COMPARE(ldr(w12, MemOperand(x13, w14, SXTW)), "ldr w12, [x13, w14, sxtw]"); in TEST()
1017 COMPARE(ldr(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
1026 COMPARE(ldr(x12, MemOperand(x13, w14, SXTW)), "ldr x12, [x13, w14, sxtw]"); in TEST()
1027 COMPARE(ldr(x15, MemOperand(x16, w17, SXTW, 3)), in TEST()
1037 COMPARE(str(w12, MemOperand(x13, w14, SXTW)), "str w12, [x13, w14, sxtw]"); in TEST()
1038 COMPARE(str(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
1047 COMPARE(str(x12, MemOperand(x13, w14, SXTW)), "str x12, [x13, w14, sxtw]"); in TEST()
[all …]
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| D | test-assembler-a64.cc | 303 __ Mvn(x15, Operand(w2, SXTW, 4)); in TEST()
562 __ Orr(x12, x0, Operand(x1, SXTW, 2)); in TEST()
656 __ Orn(x12, x0, Operand(x1, SXTW, 2)); in TEST()
723 __ And(x12, x0, Operand(x1, SXTW, 2)); in TEST()
861 __ Bic(x12, x0, Operand(x1, SXTW, 2)); in TEST()
985 __ Eor(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1052 __ Eon(x12, x0, Operand(x1, SXTW, 2)); in TEST()
2577 __ Ldr(w3, MemOperand(x18, x27, SXTW)); in TEST()
2578 __ Ldr(w4, MemOperand(x18, x28, SXTW, 2)); in TEST()
2581 __ Str(w2, MemOperand(x20, x29, SXTW, 2)); in TEST()
[all …]
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 60 SXTW); in MemoryOperand()
445 __ Add(index, object, Operand(index, SXTW)); in AssembleArchInstruction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 679 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
762 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
818 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
993 if (Addr.getExtendType() == AArch64_AM::SXTW || in simplifyAddress()
1009 else if (Addr.getExtendType() == AArch64_AM::SXTW) in simplifyAddress()
1070 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW || in addLoadStoreOperands()
1746 Addr.getExtendType() == AArch64_AM::SXTW) in emitLoad()
1995 Addr.getExtendType() == AArch64_AM::SXTW) in emitStore()
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| D | AArch64ISelDAGToDAG.cpp | 361 return AArch64_AM::SXTW; in getExtendTypeForNode()
717 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32); in SelectExtendedSHL()
787 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32); in SelectAddrModeWRO()
798 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32); in SelectAddrModeWRO()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 939 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
974 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1493 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1505 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2275 .Case("sxtw", AArch64_AM::SXTW) in tryParseOptionalShiftExtend()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 480 SXTW, enumerator
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 392 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
443 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
4828 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| D | constants-a64.h | 282 SXTW = 6, enumerator
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| D | simulator-a64.cc | 387 case SXTW: in ExtendValue()
1084 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | disasm-a64.cc | 3370 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 1264 ### SXTW ### subsection
|