| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 406 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence() local
407 if (!SchedRW.IsSequence) { in expandRWSequence()
412 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
414 for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end(); in expandRWSequence()
488 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead)); in findOrInsertRW() local
490 SchedReads.push_back(SchedRW); in findOrInsertRW()
492 SchedWrites.push_back(SchedRW); in findOrInsertRW()
960 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
983 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead); in mutuallyExclusive() local
984 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant"); in mutuallyExclusive()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSystem.td | 16 let SchedRW = [WriteSystem] in {
39 } // SchedRW
45 let SchedRW = [WriteSystem] in {
69 } // SchedRW
79 let SchedRW = [WriteSystem] in {
120 } // SchedRW
125 let SchedRW = [WriteSystem] in {
139 } // SchedRW
144 let SchedRW = [WriteSystem] in {
158 } // SchedRW
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| D | X86InstrFPStack.td | 213 let SchedRW = [WriteFAddLd] in {
218 let SchedRW = [WriteFMulLd] in {
221 let SchedRW = [WriteFDivLd] in {
237 let SchedRW = [WriteFAdd] in {
247 } // SchedRW
248 let SchedRW = [WriteFMul] in {
252 } // SchedRW
253 let SchedRW = [WriteFDiv] in {
260 } // SchedRW
279 let SchedRW = [WriteFSqrt] in {
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| D | X86InstrInfo.td | 960 let hasSideEffects = 0, SchedRW = [WriteZero] in {
973 let SchedRW = [WriteALU] in {
983 } // SchedRW
990 let mayLoad = 1, SchedRW = [WriteLoad] in {
1003 } // mayLoad, SchedRW
1005 let mayStore = 1, SchedRW = [WriteStore] in {
1031 } // mayStore, SchedRW
1035 SchedRW = [WriteLoad] in {
1043 SchedRW = [WriteStore] in {
1051 let mayLoad = 1, SchedRW = [WriteLoad] in {
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| D | X86InstrArithmetic.td | 17 let SchedRW = [WriteLEA] in {
39 } // SchedRW
154 let isCommutable = 1, SchedRW = [WriteIMul] in {
173 } // isCommutable, SchedRW
176 let SchedRW = [WriteIMulLd, ReadAfterLd] in {
198 } // SchedRW
205 let SchedRW = [WriteIMul] in {
243 } // SchedRW
246 let SchedRW = [WriteIMulLd] in {
288 } // SchedRW
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| D | X86InstrControl.td | 23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
59 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
71 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
102 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
165 let SchedRW = [WriteJump] in {
229 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
260 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
283 SchedRW = [WriteJump] in {
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| D | X86ScheduleBtVer2.td | 77 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
90 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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| D | X86InstrShiftRotate.td | 18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
66 } // Constraints = "$src = $dst", SchedRW
69 let SchedRW = [WriteShiftLd, WriteRMW] in {
122 } // SchedRW
124 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
168 } // Constraints = "$src = $dst", SchedRW
171 let SchedRW = [WriteShiftLd, WriteRMW] in {
222 } // SchedRW
224 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
279 } // Constraints = "$src = $dst", SchedRW
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| D | X86InstrMMX.td | 265 let SchedRW = [WriteMove] in {
280 } // SchedRW
288 let SchedRW = [WriteLoad] in {
294 } // SchedRW
295 let SchedRW = [WriteStore] in
301 let SchedRW = [WriteMove] in {
327 } // SchedRW
641 let SchedRW = [WriteShuffle] in {
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| D | X86ScheduleSLM.td | 59 multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
63 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
67 def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
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| D | X86SchedSandyBridge.td | 72 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
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| D | X86InstrCMovSetCC.td | 19 isCommutable = 1, SchedRW = [WriteALU] in {
41 SchedRW = [WriteALULd, ReadAfterLd] in {
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| D | X86InstrCompiler.td | 158 let SchedRW = [WriteSystem] in {
196 } // SchedRW
280 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
343 let SchedRW = [WriteMicrocoded] in {
406 } // SchedRW
550 SchedRW = [WriteALULd, WriteRMW] in {
638 SchedRW = [WriteALULd, WriteRMW] in {
672 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
693 SchedRW = [WriteALULd, WriteRMW] in {
700 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
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| D | X86InstrSSE.td | 458 isPseudo = 1, SchedRW = [WriteZero] in {
475 isPseudo = 1, SchedRW = [WriteZero] in {
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
530 isPseudo = 1, SchedRW = [WriteZero] in {
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
901 } // SchedRW
905 SchedRW = [WriteFShuffle] in {
961 let SchedRW = [WriteStore] in {
978 } // SchedRW
982 SchedRW = [WriteFShuffle] in {
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| D | X86SchedHaswell.td | 82 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
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| D | X86InstrAVX512.td | 2114 SchedRW = [WriteLoad] in
2129 let mayLoad = 1, SchedRW = [WriteLoad] in
2139 let mayLoad = 1, SchedRW = [WriteLoad] in
2779 let SchedRW = [WriteLoad] in {
2804 let SchedRW = [WriteStore], mayStore = 1,
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrFormats.td | 73 let SchedRW = [Write32Bit];
223 let SchedRW = [WriteSALU] in {
285 } // let SchedRW = [WriteSALU]
296 let SchedRW = [WriteSMEM];
615 let SchedRW = [WriteLDS];
628 let SchedRW = [WriteVMEM];
640 let SchedRW = [WriteVMEM];
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| D | SIInstructions.td | 1243 // FIXME: Specify SchedRW for READFIRSTLANE_B32
1255 let SchedRW = [WriteQuarterRate32] in {
1312 } // let SchedRW = [WriteQuarterRate32]
1333 let SchedRW = [WriteQuarterRate32] in {
1348 } //let SchedRW = [WriteQuarterRate32]
1350 let SchedRW = [WriteDouble] in {
1359 } // let SchedRW = [WriteDouble];
1365 let SchedRW = [WriteDouble] in {
1371 } // let SchedRW = [WriteDouble]
1409 let SchedRW = [WriteQuarterRate32] in {
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 94 // that have a scheduling class (itinerary class or SchedRW list)
204 list<SchedReadWrite> SchedRW = schedrw;
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| D | Target.td | 432 list<SchedReadWrite> SchedRW;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2409 let SchedRW = [WriteFDiv] in {
2418 let SchedRW = [WriteFDiv] in {
2425 let SchedRW = [WriteFMul] in {
|