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Searched refs:ShOp (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
DARMMCCodeEmitter.cpp1084 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1085 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1137 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1139 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1664 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
1667 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2262 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2279 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2287 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2288 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2289 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2298 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2325 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2572 ValueType Ty, SDNode ShOp>
2577 (Ty (ShOp (Ty DPR:$Vn),
2584 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2589 (Ty (ShOp (Ty DPR:$Vn),
2620 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2625 (ResTy (ShOp (ResTy QPR:$Vn),
2633 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2638 (ResTy (ShOp (ResTy QPR:$Vn),
2780 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2787 (Ty (ShOp (Ty DPR:$src1),
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp2066 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
2067 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
2073 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
2075 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2077 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
2078 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2084 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
2086 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
DDAGCombiner.cpp2648 SDValue ShOp = N0->getOperand(1); in SimplifyBinOpWithSameOpcodeHands() local
2652 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) { in SimplifyBinOpWithSameOpcodeHands()
2654 ShOp = DAG.getConstant(0, VT); in SimplifyBinOpWithSameOpcodeHands()
2656 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
2662 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in SimplifyBinOpWithSameOpcodeHands()
2666 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp, in SimplifyBinOpWithSameOpcodeHands()
2672 ShOp = N0->getOperand(0); in SimplifyBinOpWithSameOpcodeHands()
2673 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) { in SimplifyBinOpWithSameOpcodeHands()
2675 ShOp = DAG.getConstant(0, VT); in SimplifyBinOpWithSameOpcodeHands()
2677 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1590 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1593 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1596 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1599 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1602 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1606 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1607 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1615 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1617 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()