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Searched refs:ShiftAmt (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/lib/Transforms/Scalar/
DBDCE.cpp158 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1); in determineLiveOperandBits() local
159 AB = AOut.lshr(ShiftAmt); in determineLiveOperandBits()
165 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in determineLiveOperandBits()
167 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in determineLiveOperandBits()
174 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1); in determineLiveOperandBits() local
175 AB = AOut.shl(ShiftAmt); in determineLiveOperandBits()
180 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt); in determineLiveOperandBits()
187 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1); in determineLiveOperandBits() local
188 AB = AOut.shl(ShiftAmt); in determineLiveOperandBits()
192 if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt)) in determineLiveOperandBits()
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DGVN.cpp1138 unsigned ShiftAmt; in GetStoreValueForLoad() local
1140 ShiftAmt = Offset*8; in GetStoreValueForLoad()
1142 ShiftAmt = (StoreSize-LoadSize-Offset)*8; in GetStoreValueForLoad()
1144 if (ShiftAmt) in GetStoreValueForLoad()
1145 SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt); in GetStoreValueForLoad()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp651 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
652 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); in SimplifyDemandedUseBits()
657 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in SimplifyDemandedUseBits()
659 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in SimplifyDemandedUseBits()
665 KnownZero <<= ShiftAmt; in SimplifyDemandedUseBits()
666 KnownOne <<= ShiftAmt; in SimplifyDemandedUseBits()
668 if (ShiftAmt) in SimplifyDemandedUseBits()
669 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); in SimplifyDemandedUseBits()
675 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
678 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); in SimplifyDemandedUseBits()
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DInstCombineCasts.cpp567 uint32_t ShiftAmt = KnownZeroMask.logBase2(); in transformZExtICmp() local
569 if (ShiftAmt) { in transformZExtICmp()
572 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt), in transformZExtICmp()
709 uint64_t ShiftAmt = Amt->getZExtValue(); in CanEvaluateZExtd() local
710 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0; in CanEvaluateZExtd()
944 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); in transformSExtICmp() local
946 if (ShiftAmt) in transformSExtICmp()
948 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
958 unsigned ShiftAmt = KnownZeroMask.countLeadingZeros(); in transformSExtICmp() local
960 if (ShiftAmt) in transformSExtICmp()
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/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp76 const unsigned ShiftAmt = ToIdx * 16; in replicateChunk() local
79 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt; in replicateChunk()
81 Imm &= ~(0xFFFFLL << ShiftAmt); in replicateChunk()
93 const unsigned ShiftAmt = ChunkIdx * 16; in tryOrrMovk() local
113 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryOrrMovk()
174 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
177 for (; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
178 Imm16 = (UImm >> ShiftAmt) & 0xFFFF; in tryToreplicateChunks()
191 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
202 for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) { in tryToreplicateChunks()
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DAArch64ISelDAGToDAG.cpp244 unsigned ShiftAmt; in SelectArithImmed() local
247 ShiftAmt = 0; in SelectArithImmed()
249 ShiftAmt = 12; in SelectArithImmed()
254 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed()
1703 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
1704 Mask = Mask.shl(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
1706 Mask = Mask.lshr(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
1711 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
1712 Mask = Mask.lshr(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
1714 Mask = Mask.shl(ShiftAmt); in getUsefulBitsFromOrWithShiftedReg()
/external/llvm/lib/Analysis/
DValueTracking.cpp1197 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in computeKnownBits() local
1199 KnownZero <<= ShiftAmt; in computeKnownBits()
1200 KnownOne <<= ShiftAmt; in computeKnownBits()
1201 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0 in computeKnownBits()
1208 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in computeKnownBits() local
1212 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); in computeKnownBits()
1213 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); in computeKnownBits()
1215 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in computeKnownBits()
1222 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in computeKnownBits() local
1226 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); in computeKnownBits()
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DConstantFolding.cpp176 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); in FoldBitCast() local
187 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
188 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; in FoldBitCast()
208 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); in FoldBitCast() local
213 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
214 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize; in FoldBitCast()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1316 unsigned ShiftAmt; in emitIntSExt32r1() local
1321 ShiftAmt = 24; in emitIntSExt32r1()
1324 ShiftAmt = 16; in emitIntSExt32r1()
1328 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1329 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
DMipsISelLowering.cpp1160 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() local
1215 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in emitAtomicBinaryPartword()
1220 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); in emitAtomicBinaryPartword()
1225 .addReg(MaskUpper).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1227 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1288 .addReg(MaskedOldVal1).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1395 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() local
1457 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in emitAtomicCmpSwapPartword()
1462 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); in emitAtomicCmpSwapPartword()
1467 .addReg(MaskUpper).addReg(ShiftAmt); in emitAtomicCmpSwapPartword()
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/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp846 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in FoldMaskedShiftToScaledMask() local
847 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) in FoldMaskedShiftToScaledMask()
852 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT); in FoldMaskedShiftToScaledMask()
866 AM.Scale = 1 << ShiftAmt; in FoldMaskedShiftToScaledMask()
906 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in FoldMaskAndShiftToScale() local
923 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt; in FoldMaskAndShiftToScale()
958 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8); in FoldMaskAndShiftToScale()
DX86ISelLowering.cpp6694 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1); in lowerVectorShuffleAsShift() local
6707 V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8)); in lowerVectorShuffleAsShift()
14520 SDValue SrcOp, uint64_t ShiftAmt, in getTargetVShiftByConstNode() argument
14525 if (ShiftAmt == 0) in getTargetVShiftByConstNode()
14529 if (ShiftAmt >= ElementType.getSizeInBits()) { in getTargetVShiftByConstNode()
14531 ShiftAmt = ElementType.getSizeInBits() - 1; in getTargetVShiftByConstNode()
14558 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType)); in getTargetVShiftByConstNode()
14570 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType)); in getTargetVShiftByConstNode()
14582 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType)); in getTargetVShiftByConstNode()
14590 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8)); in getTargetVShiftByConstNode()
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/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp880 unsigned ShiftAmt = V.getConstantOperandVal(1); in getValueBits() local
885 for (unsigned i = ShiftAmt; i < Bits.size(); ++i) in getValueBits()
886 Bits[i] = LHSBits[i - ShiftAmt]; in getValueBits()
888 for (unsigned i = 0; i < ShiftAmt; ++i) in getValueBits()
896 unsigned ShiftAmt = V.getConstantOperandVal(1); in getValueBits() local
901 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i) in getValueBits()
902 Bits[i] = LHSBits[i + ShiftAmt]; in getValueBits()
904 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i) in getValueBits()
2399 SDValue ShiftAmt = in Select() local
2405 N0, ShiftAmt); in Select()
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DPPCISelLowering.cpp1238 unsigned ShiftAmt = SVOp->getMaskElt(i); in isVSLDOIShuffleMask() local
1239 if (ShiftAmt < i) return -1; in isVSLDOIShuffleMask()
1241 ShiftAmt -= i; in isVSLDOIShuffleMask()
1247 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) in isVSLDOIShuffleMask()
1252 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) in isVSLDOIShuffleMask()
1258 ShiftAmt = 16 - ShiftAmt; in isVSLDOIShuffleMask()
1260 return ShiftAmt; in isVSLDOIShuffleMask()
1428 unsigned ShiftAmt = SVOp->getMaskElt(i); in isQVALIGNIShuffleMask() local
1429 if (ShiftAmt < i) return -1; in isQVALIGNIShuffleMask()
1430 ShiftAmt -= i; in isQVALIGNIShuffleMask()
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/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1563 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1); in executeBitCastInst() local
1569 Tmp = Tmp.shl(ShiftAmt); in executeBitCastInst()
1570 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; in executeBitCastInst()
1579 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1); in executeBitCastInst() local
1584 Elt.IntVal = Elt.IntVal.lshr(ShiftAmt); in executeBitCastInst()
1588 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize; in executeBitCastInst()
/external/clang/lib/CodeGen/
DCGBuiltin.cpp1940 int ShiftAmt = cast<ConstantInt>(Shift)->getSExtValue(); in EmitNeonRShiftImm() local
1947 if (ShiftAmt == EltSize) { in EmitNeonRShiftImm()
1955 --ShiftAmt; in EmitNeonRShiftImm()
1956 Shift = ConstantInt::get(VTy->getElementType(), ShiftAmt); in EmitNeonRShiftImm()
2770 Constant *ShiftAmt = ConstantInt::get(SrcTy->getElementType(), in EmitCommonNeonBuiltinExpr() local
2772 ShiftAmt = ConstantVector::getSplat(VTy->getNumElements(), ShiftAmt); in EmitCommonNeonBuiltinExpr()
2773 Ops[0] = Builder.CreateLShr(Ops[0], ShiftAmt, "vaddhn"); in EmitCommonNeonBuiltinExpr()
3089 Constant *ShiftAmt = ConstantInt::get(SrcTy->getElementType(), in EmitCommonNeonBuiltinExpr() local
3091 ShiftAmt = ConstantVector::getSplat(VTy->getNumElements(), ShiftAmt); in EmitCommonNeonBuiltinExpr()
3092 Ops[0] = Builder.CreateLShr(Ops[0], ShiftAmt, "vsubhn"); in EmitCommonNeonBuiltinExpr()
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/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp3122 uint32_t ShiftAmt = 0, MaxShiftAmt = IsXReg ? 48 : 16; in parseOperand() local
3124 ShiftAmt += 16; in parseOperand()
3127 if (ShiftAmt <= MaxShiftAmt && Imm <= 0xFFFF) { in parseOperand()
3131 if (ShiftAmt) in parseOperand()
3133 ShiftAmt, true, S, E, Ctx)); in parseOperand()
3136 APInt Simm = APInt(64, Imm << ShiftAmt); in parseOperand()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp1457 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerLOAD() local
1460 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt); in LowerLOAD()
1515 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerSTORE() local
1524 MaskedValue, ShiftAmt); in LowerSTORE()
1527 ShiftAmt); in LowerSTORE()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp814 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); in SimplifyDemandedBits() local
817 ShiftAmt)); in SimplifyDemandedBits()
2874 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); in expandMUL() local
2875 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT)); in expandMUL()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp4801 uint64_t ShiftAmt = ShiftCnst->getZExtValue(); in SelectBFE() local
4824 NumBits = countTrailingOnes(MaskVal) - ShiftAmt; in SelectBFE()
4831 NumBits = NumZeros + NumOnes - ShiftAmt; in SelectBFE()
4837 if (ShiftAmt < NumZeros) { in SelectBFE()
4844 Start = CurDAG->getTargetConstant(ShiftAmt, MVT::i32); in SelectBFE()
DNVPTXISelLowering.cpp4132 APInt ShiftAmt = ShlRHS->getAPIntValue(); in TryMULWIDECombine() local
4134 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) { in TryMULWIDECombine()
4135 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt; in TryMULWIDECombine()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2738 SDValue ShiftAmt = DAG.getConstant(63, VT); in LowerUMULO_SMULO() local
2741 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO()
2742 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
2753 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO()
/external/llvm/lib/Transforms/Utils/
DSimplifyCFG.cpp3861 Value *ShiftAmt = Builder.CreateZExtOrTrunc(Index, MapTy, "switch.cast"); in BuildLookup() local
3864 ShiftAmt = Builder.CreateMul(ShiftAmt, in BuildLookup()
3869 Value *DownShifted = Builder.CreateLShr(BitMap, ShiftAmt, in BuildLookup()
/external/llvm/lib/Support/
DAPInt.cpp2246 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
2252 Tmp = Tmp.lshr(ShiftAmt); in toString()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp8118 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt); in PerformMULCombine() local
8120 ShiftAmt = ShiftAmt & (32 - 1); in PerformMULCombine()
8125 MulAmt >>= ShiftAmt; in PerformMULCombine()
8171 if (ShiftAmt != 0) in PerformMULCombine()
8173 Res, DAG.getConstant(ShiftAmt, MVT::i32)); in PerformMULCombine()

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