Searched refs:ShiftOp (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineShifts.cpp | 542 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); in FoldShiftByConstant() local
543 if (ShiftOp && !ShiftOp->isShift()) in FoldShiftByConstant()
544 ShiftOp = nullptr; in FoldShiftByConstant()
546 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { in FoldShiftByConstant()
560 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); in FoldShiftByConstant()
565 Value *X = ShiftOp->getOperand(0); in FoldShiftByConstant()
570 if (I.getOpcode() == ShiftOp->getOpcode()) { in FoldShiftByConstant()
587 ShiftOp->getOpcode() == Instruction::Shl) { in FoldShiftByConstant()
599 ShiftOp->getOpcode() != Instruction::Shl && in FoldShiftByConstant()
600 ShiftOp->isExact()) { in FoldShiftByConstant()
[all …]
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| /external/v8/src/arm/ |
| D | constants-arm.h | 228 enum ShiftOp { enum
558 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } in ShiftValue()
559 inline ShiftOp ShiftField() const { in ShiftField()
560 return static_cast<ShiftOp>(BitField(6, 5)); in ShiftField()
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| D | assembler-arm.h | 502 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
516 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
542 ShiftOp shift_op() const { return shift_op_; } in shift_op()
547 ShiftOp shift_op_;
575 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
605 ShiftOp shift_op_;
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| D | disasm-arm.cc | 191 ShiftOp shift = instr->ShiftField(); in PrintShiftRm()
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| D | assembler-arm.cc | 281 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { in Operand()
302 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { in Operand()
329 ShiftOp shift_op, int shift_imm, AddrMode am) { in MemOperand()
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| D | simulator-arm.cc | 1349 ShiftOp shift = instr->ShiftField(); in GetShiftRm()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 711 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
712 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
713 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 2148 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
2153 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2154 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
2156 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| D | SelectionDAGBuilder.cpp | 1945 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), in visitBitTestCase() local
1954 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp, in visitBitTestCase()
1959 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp, in visitBitTestCase()
1964 DAG.getConstant(1, VT), ShiftOp); in visitBitTestCase()
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