Searched refs:ShiftReg (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 1255 unsigned ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1275 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1282 .addReg(ShiftReg); in EmitShiftInstr()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 513 unsigned ShiftReg; member
1807 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2620 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2625 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
2915 << " " << RegShiftedReg.ShiftReg << ">"; in print()
3081 int ShiftReg = 0; in tryParseShiftRegister() local
3086 ShiftReg = SrcReg; in tryParseShiftRegister()
3121 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3122 if (ShiftReg == -1) { in tryParseShiftRegister()
3133 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 7956 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8001 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
8010 .addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
8018 .addReg(Mask2Reg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
8043 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
8672 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
8727 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
8736 .addReg(newval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
8738 .addReg(oldval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
8747 .addReg(Mask2Reg).addReg(ShiftReg); in EmitInstrWithCustomInserter()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3588 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, in fastLowerIntrinsicCall() local
3592 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3594 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, in fastLowerIntrinsicCall()
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