Home
last modified time | relevance | path

Searched refs:Src0RC (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp320 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
322 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
325 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
DSIInstrInfo.cpp1764 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
1765 if (DstRC != Src0RC) { in legalizeOperands()
2338 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
2342 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
2344 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
2354 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
2391 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp() local
2395 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
2402 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()
2415 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()
DSIInstrInfo.td838 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
839 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
840 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
845 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
853 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
857 (ins Src0RC:$src0)
862 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
867 (ins Src0RC:$src0, Src1RC:$src1)
872 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
878 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)