| /external/llvm/lib/Linker/ |
| D | LinkModules.cpp | 1321 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1323 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1324 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1334 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1335 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1342 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1343 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1356 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1363 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1364 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
[all …]
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 241 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
242 if (SrcOp > DestOp) { in ParseConstraint()
243 std::swap(SrcOp, DestOp); in ParseConstraint()
247 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 938 const MachineOperand &SrcOp, in getShuffleComment() argument
952 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem"; in getShuffleComment()
1165 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1172 OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask)); in EmitInstruction()
1185 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1192 OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask)); in EmitInstruction()
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| D | X86ISelLowering.cpp | 4665 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, in getVShift() argument
4671 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); in getVShift()
4672 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType()); in getVShift()
4676 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
4680 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) { in LowerAsSplatVectorLoad() argument
4685 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { in LowerAsSplatVectorLoad()
14520 SDValue SrcOp, uint64_t ShiftAmt, in getTargetVShiftByConstNode() argument
14526 return SrcOp; in getTargetVShiftByConstNode()
14541 if (VT == SrcOp.getSimpleValueType() && in getTargetVShiftByConstNode()
14542 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) { in getTargetVShiftByConstNode()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 149 MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
674 MachineInstr *HexagonExpandCondsets::genTfrFor(MachineOperand &SrcOp, in genTfrFor() argument
676 MachineInstr *MI = SrcOp.getParent(); in genTfrFor()
687 unsigned Opc = getCondTfrOpcode(SrcOp, Cond); in genTfrFor()
691 .addOperand(SrcOp); in genTfrFor()
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 707 const MachineOperand &SrcOp = MI->getOperand(1); in expandPostRAPseudo() local
709 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
710 if (SrcOp.isImm()) { in expandPostRAPseudo()
711 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
719 assert(SrcOp.isReg()); in expandPostRAPseudo()
721 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
724 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 1909 Value *SrcOp = Instr->getOperand(op); in scalarizeInstruction() local
1912 if (SrcOp == OldInduction) { in scalarizeInstruction()
1913 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
1918 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
1929 Scalars.append(UF, SrcOp); in scalarizeInstruction()
5252 Value *SrcOp = Instr->getOperand(op); in scalarizeInstruction() local
5255 if (SrcOp == OldInduction) { in scalarizeInstruction()
5256 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
5261 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
5272 Scalars.append(UF, SrcOp); in scalarizeInstruction()
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| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2362 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
2363 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
2372 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
2379 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2392 SrcOp, RI->getOperand(0), Q, in SimplifyICmpInst()
2408 SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2451 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2466 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2498 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
2507 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
1775 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, in EmitStackConvert() argument
1781 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType(). in EmitStackConvert()
1789 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); in EmitStackConvert()
1800 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
1804 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
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