Searched refs:SrcR1 (Results 1 – 1 of 1) sorted by relevance
275 const unsigned SrcR1 = MI->getOperand(1).getReg(); in processInstructionForSLM() local277 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) in processInstructionForSLM()303 if (SrcR1 != 0 && SrcR2 != 0) { in processInstructionForSLM()304 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM()305 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM()315 const MachineOperand &SrcR = MI->getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM()