| /external/llvm/lib/Target/R600/ |
| D | SILowerI1Copies.cpp | 107 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
110 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
137 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
|
| D | SIFixSGPRCopies.cpp | 191 const TargetRegisterClass *SrcRC; in isVGPRToSGPRCopy() local
198 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); in isVGPRToSGPRCopy()
199 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
|
| D | SIInstrInfo.cpp | 2452 const TargetRegisterClass *SrcRC = Src.isReg() ? in splitScalar64BitBCNT() local
2459 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
2461 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, in splitScalar64BitBCNT()
2463 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, in splitScalar64BitBCNT()
|
| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 514 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
517 if (DefRC == SrcRC) in shareSameRegisterFile()
523 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
529 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
534 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
536 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
577 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src); in findNextSource() local
580 ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, DefSubReg, SrcRC, in findNextSource()
|
| D | RegisterCoalescer.cpp | 332 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
341 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
348 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
352 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
355 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
370 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1242 auto SrcRC = MRI->getRegClass(CP.getSrcReg()); in joinCopy() local
1248 std::swap(SrcRC, DstRC); in joinCopy()
1250 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx, in joinCopy()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 99 const TargetRegisterClass *SrcRC = in processBlock() local
106 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
146 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
151 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
156 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
|
| D | MipsInstrInfo.td | 938 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
939 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
940 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
949 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
950 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
951 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
|
| D | MipsDSPInstrInfo.td | 1279 RegisterClass SrcRC> :
1280 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1281 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (DestRC != SrcRC) in copyPhysReg()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrMMX.td | 185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
196 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
|
| D | X86InstrAVX512.td | 632 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
635 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
636 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
724 RegisterClass SrcRC> {
726 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
731 RegisterClass SrcRC, Predicate prd> {
733 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
735 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
736 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
3880 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
[all …]
|
| D | X86InstrSSE.td | 1480 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1484 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1491 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1495 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1503 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1506 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1640 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1643 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1645 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
[all …]
|
| D | X86FastISel.cpp | 1042 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in X86SelectRet() local
1044 if (!SrcRC->contains(DstReg)) in X86SelectRet()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 182 const TargetRegisterClass *SrcRC,
|
| D | ARMBaseRegisterInfo.cpp | 767 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
780 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) in shouldCoalesce()
786 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
|
| D | ARMFastISel.cpp | 2142 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); in SelectRet() local
2144 if (!SrcRC->contains(DstReg)) in SelectRet()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 390 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
393 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
398 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
|
| D | InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
171 if (MatchReg && SrcRC->getCopyCost() < 0) { in EmitCopyFromReg()
|
| D | ScheduleDAGRRList.cpp | 1138 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
1141 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
1146 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 842 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
|